Inter-Core Communication Queue Offload for Multi-Core Processors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing inter-core communication technologies for multi-core processors require CPU involvement in operations like message copying, queue space maintenance, and message channel access arbitration, leading to increased thread occupancy and reduced CPU performance.
Innovation Solution
An inter-core communication system that utilizes a memory management module and queue management module to handle message data and space management, with descriptor pointer applications processed without CPU intervention, using a shared memory plus interrupt service mechanism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the mailbox module is used for inter-core communication with CPU participation, then message transmission can be achieved, but CPU occupancy increases and performance decreases
Solution Approach 1:
The patent extracts the CPU from the message transmission process by introducing a dedicated inter-core communication device that independently handles message copying, queue management, and channel arbitration. The CPU only needs to send messages to the communication device, which then autonomously manages the entire transmission process between cores, eliminating the need for CPU participation in routine communication operations.
Solution Approach 2:
The inter-core communication device provides self-service functionality by automatically managing message queues, performing copy operations, and arbitrating channel access without CPU intervention. The device includes dedicated hardware components that autonomously handle communication tasks, allowing the system to maintain reliable inter-core communication while freeing CPU resources for computational work.
2Adaptability or versatility
If the CPU participates in message copying and queue maintenance operations, then communication functionality is maintained, but thread occupancy increases
Solution Approach 1:
The patent segments the communication system into distinct functional components: the CPU sends messages to a dedicated inter-core communication device that independently handles message copying, queue maintenance, and transmission. This segmentation allows the CPU to complete its task quickly without being occupied by subsequent communication operations, while the communication device autonomously manages the segmented communication sub-tasks.
Solution Approach 2:
The inter-core communication device acts as an intermediary between the CPU and the message queue system. Instead of the CPU directly managing messages and queues, it interacts with the communication device, which then handles all queue operations and message transmissions. This intermediary approach maintains full communication functionality while eliminating CPU thread occupancy during communication operations.
3Ease of operation
If the CPU performs message channel access arbitration, then channel management is achieved, but CPU performance is reduced
Solution Approach 1:
The patent extracts the channel arbitration function from the CPU and implements it within the inter-core communication device. The communication device includes dedicated arbitration logic that automatically manages channel access between different message queues and cores, eliminating the need for CPU participation in arbitration decisions while maintaining proper channel management and access control.
Data Source
AI summary
Disclosed are an inter-core communication system, method and device for a multi-core processor and a storage medium. The system includes: an inter-core communication device connected to multiple systems. The multiple systems include a first system and a second system. The inter-core communication device includes: a memory management module configured to receive a descriptor application instruction sent by the first system and determine a descriptor pointer corresponding to the descriptor application instruction, the first system stores data to be transmitted in the memory corresponding to the descriptor pointer; a queue management module configured to enqueue the descriptor pointer to the specified queue after receiving an enqueue application sent by the first system; an interrupt module configured to dequeue a descriptor in the specified queue through an interrupt service program of the second system after the number of times of enqueues corresponding to the specified queue reaches a preset threshold.