Inter-Die Data Transfer Using Bit-Wise Asynchronous Sampling
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Solution Overview
Problem
Existing inter-die data transfer systems face limitations such as limited crossing frequency in synchronous systems and low throughput in asynchronous systems due to factors like PVT variations, clock skew, and the need for additional wires and handshaking.
Innovation Solution
A bit-wise asynchronous inter-die data transfer system that includes a receiver circuit with a safe sample selection circuit and a latency adjustment circuit, which performs a training phase to determine safe sample selection and latency adjustment signals, allowing for high-frequency data transfer with configurable bus width and high throughput without additional wires or handshaking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous system is used for inter-die data transfer, then timing reliability is improved, but crossing frequency is limited due to PVT variations and clock skew
Solution Approach 1:
The patent segments the data transfer into bit-parallel channels, where each bit can be transferred independently through dedicated wires. This segmentation allows asynchronous operation for each bit while maintaining overall synchronization through the bit-parallel structure, resolving the contradiction between timing reliability and crossing frequency.
Solution Approach 2:
The patent implements dynamic sampling where the receiver samples data at optimally determined times based on actual signal conditions rather than fixed clock edges. The sampling circuit adjusts sampling timing dynamically to account for PVT variations, enabling higher crossing frequencies while maintaining timing reliability.
2Reliability
If asynchronous die crossing system uses additional crossing wires and handshake, then reliability is improved, but throughput is reduced
Solution Approach 1:
The patent segments the data transfer into bit-parallel channels, eliminating the need for additional crossing wires by using the existing bus wires for direct bit transmission. Each bit has its own dedicated wire, removing the handshake protocol requirement and improving throughput while maintaining reliability through the bit-parallel asynchronous structure.
Solution Approach 2:
The patent extracts and removes the handshake protocol and additional crossing wires from the asynchronous die crossing system. By using bit-parallel direct transmission, the system achieves reliability without these additional components, thereby improving throughput.
3Productivity
If asynchronous FIFO is divided into two dies, then data transfer capability is improved, but device complexity increases due to more wires for addressing
Solution Approach 1:
The patent segments the addressing function into the bit-parallel structure itself, where each bit position naturally identifies its destination. This eliminates the need for separate addressing wires, reducing device complexity while maintaining data transfer capability.
Solution Approach 2:
The patent makes the data wires serve dual purposes: both data transmission and addressing identification. The bit-parallel structure provides both data carry and bit position identification, eliminating the need for dedicated addressing wires and reducing overall device complexity.
4Device complexity
If fixed data width is used in asynchronous die crossing system, then simplicity is maintained, but adaptability is reduced
Solution Approach 1:
The patent implements dynamic data width configuration where the number of active bit-parallel channels can be adjusted based on data width requirements. The system can dynamically activate or deactivate channels to match different data widths, maintaining simplicity through the bit-parallel structure while achieving adaptability.
Solution Approach 2:
The patent segments the data transfer into reusable bit-parallel channels that can be selectively activated. This segmentation allows the system to adapt to different data widths by activating the appropriate number of channels, maintaining structural simplicity while achieving configurability.
Data Source
AI summary
An inter-die data transfer system includes a receiver circuit in a receiver die coupled to a sender circuit in a sender die through a bus. The receiver circuit includes a safe sample selection circuit and a latency adjustment circuit. The safe sample selection circuit receives from the sender circuit a plurality of training data signals, and determines a safe sample selection signal for a first bit of the bus. The latency adjustment circuit determines a latency adjustment selection signal for the first bit of the bus. A user data safe sample is selected using the safe sample selection signal from a plurality of user data samples associated with a first user data input signal associated with the first bit of the bus. Latency adjustment is performed to the user data safe sample to generate a first user data output signal using the latency adjustment selection signal.