Self-Timed Inter-Die Delay Detection Circuit
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Solution Overview
Problem
Testing for delay defects in inter-die interconnections of 3D stacked ICs is challenging due to the need for complex timing synchronization between dies from different design teams, which is difficult to implement effectively.
Innovation Solution
A test circuitry that includes an input port, data storage, a feedback loop, a data conditioner, a clock pulse generator, and selection logic to determine transition delay defects without requiring synchronization between dies, allowing for self-timed operation and flexible delay settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex timing synchronization between dies is implemented to test delay defects, then measurement precision improves, but device complexity increases
Solution Approach 1:
The test circuitry uses self-timed operation where the delay measurement is performed without requiring external synchronization signals between dies. The circuit autonomously generates and measures delay using its own internal clock and feedback mechanisms, eliminating the need for complex inter-die synchronization infrastructure.
Solution Approach 2:
A feedback loop is introduced as an intermediary mechanism that carries the test signal from the output back to the input of the same die. This feedback path allows the circuit to measure inter-die delay by comparing the original signal with the returned signal, avoiding direct synchronization requirements between separate dies.
2Measurement precision
If fast functional clocks are used for delay testing, then measurement precision improves, but use of energy increases
Solution Approach 1:
The test circuitry employs periodic clock pulses instead of continuous fast clocks. The clock pulse generator produces discrete timing signals at the required frequency only during measurement intervals, allowing accurate transition delay detection while significantly reducing average power consumption compared to continuous high-speed clock operation.
3Measurement precision
If dedicated test infrastructure is added for delay testing, then measurement precision improves, but device complexity increases
Solution Approach 1:
The test circuitry is designed to perform multiple functions: it can test inter-die delay defects, verify interconnect integrity, and characterize signal propagation characteristics. By consolidating these testing capabilities into a single integrated circuit block, the solution provides comprehensive delay testing without proportionally increasing device complexity.
Solution Approach 2:
The test signal path is merged with the existing inter-die interconnect structure. The feedback loop reuses the same physical interconnect that carries functional signals, allowing delay measurement without adding separate dedicated test wires or interconnects. This merging approach enables delay testing while minimizing additional area overhead.
Data Source
Figure 1(a)~1(b)
Figure 2
Figure 3
AI summary
Test circuitry (30) for testing for transition delay defects in inter-die interconnects in a structure comprising at least a first die (Die 1) and a second die (Die 2) electrically connected to one another by means of at least a first inter-die interconnect (interconnect 1), comprises - an input port for receiving a test data value, - a data storage element (33) for temporarily storing the test data value, - at least for the first inter-die interconnect (interconnect 1) to be tested, a further inter-die interconnect (interconnect 2) arranged for being electrically connected (32) to the first inter-die interconnect (interconnect 1) so as to form a feedback loop for transferring the test data value from the data storage element (33) back to the data storage element (33), - a data conditioner for conditioning the fed back test data value so as to make it distinguishable from the stored test data value, - a clock pulse generator (36) for generating a delayed clock pulse, - selection logic for applying the generated delayed clock pulse and the conditioned fed back test data value to the data storage element, and - readout means for reading out a test data value stored in the data storage element (33).