Inter-Die Fabric Extension for ASIC Access to FPGA Resources
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Solution Overview
Problem
Current silicon stacked interconnect technology does not provide efficient techniques for coupling application-specific integrated circuit (ASIC) dies to off-die resources such as FPGA fabric and hardened IP blocks, which are essential for adaptive computing applications.
Innovation Solution
The implementation of inter-die fabric extension connections that couple a fabric sliver in the ASIC to the programmable logic fabric in another die, effectively extending the programmable logic fabric and allowing hardened IP blocks in the ASIC to utilize resources in the FPGA or another ASIC, while also providing a hardened chip-to-chip interface for communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hardened IP blocks are used in ASIC die to meet specific performance targets, then performance and reliability are improved, but device complexity and area occupation increase as hardened IP blocks may occupy most of or even the entire reticle-sized die
Solution Approach 1:
The system divides the computing resources into separate segments: hardened IP blocks are placed on an ASIC die while programmable logic fabric is placed on a separate FPGA die. This segmentation allows each die to be optimized for its specific function without competing for the same area, resolving the contradiction between performance reliability and device complexity.
Solution Approach 2:
The invention extends the programmable logic fabric across multiple dies using die-to-die interconnects, effectively adding a spatial dimension to the fabric architecture. This allows the fabric to expand beyond a single reticle-sized die, enabling hardened IP blocks to occupy full ASIC dies while fabric resources are distributed across additional FPGA dies.
2Adaptability or versatility
If programmable logic fabric is extended to multiple dies to increase functionality, then adaptability and versatility are improved, but device complexity and interconnect requirements increase
Solution Approach 1:
The system introduces a standardized die-to-die interconnect interface as an intermediary between ASIC and FPGA dies. This intermediary provides a clean, well-defined communication protocol that simplifies the complexity of multi-die integration, allowing fabric extension while maintaining manageable device complexity through standardized interfaces.
3Reliability
If current die-to-die interconnect solutions are used to connect ASIC to FPGA fabric, then basic communication is achieved, but communication efficiency and bandwidth are insufficient for adaptive computing applications
Solution Approach 1:
The die-to-die interconnect is designed with universal functionality that supports both traditional ASIC-to-FPGA communication and extended fabric connectivity. This multi-functional interface achieves high communication efficiency by providing dedicated fabric extension channels while maintaining backward compatibility with standard die-to-die communication protocols.
Data Source
AI summary
Embodiments herein describe connecting an ASIC to another integrated circuit (or die) using inter-die connections. In one embodiment, an ASIC includes a fabric sliver (e.g., a small region of programmable logic circuitry). Inter-die fabric extension connections are used to connect the fabric sliver in the ASIC to fabric (e.g., programmable logic) in the other integrated circuit. These connections effectively extend the fabric in the ASIC to include the fabric in the other integrated circuit. Hardened IP blocks in the ASIC can then use the fabric sliver and the inter-die extension connections to access computer resources in the other integrated circuit.