Inter-Die Gap Fill Structure for Crack-Resistant SoC Dicing
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Solution Overview
Problem
Existing system-on-chip (SoC) architectures face defects and performance issues due to crack formation and propagation in the inter-die gaps during dicing operations, which can lead to reliability and functionality problems.
Innovation Solution
A conformal protection layer is formed over the sidewalls of semiconductor chips using atomic layer deposition, followed by gap filling with dielectric materials to prevent crack initiation and propagation, using processes like chemical vapor deposition and chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dicing operations are performed to separate individual chips from the semiconductor wafer, then productivity is improved by enabling chip packaging, but cracks and defects form in the inter-die gaps causing reliability issues
Solution Approach 1:
A gap fill dielectric layer is formed in the inter-die gaps between adjacent die before dicing operations are performed. This preliminary action prevents crack formation during the subsequent dicing process by providing structural support and stress relief in the gap regions, thereby enabling productivity improvement without compromising reliability.
Solution Approach 2:
The gap fill dielectric material acts as a cushioning layer that absorbs and distributes mechanical stresses during dicing operations. By placing this protective layer beforehand in the inter-die gaps, the structure is prepared to withstand the cutting forces without developing cracks that would propagate into the die, thus maintaining reliability while enabling chip separation for packaging.
2Reliability
If gap fill dielectric material is deposited to fill inter-die gaps, then crack propagation is prevented improving reliability, but process complexity increases due to additional deposition and planarization steps
Solution Approach 1:
The gap filling process is segmented into distinct sequential steps: first forming the gap fill dielectric layer through CVD or spin-on-glass deposition, then performing CMP planarization to restore the surface. This segmentation allows each step to be optimized independently and integrated into existing manufacturing workflows, managing complexity while achieving reliable crack prevention.
Solution Approach 2:
The gap fill dielectric material serves as an intermediary layer between the die and the dicing process. This intermediate structure mediates the mechanical stresses during cutting, preventing direct stress transmission to the die edges. The use of standard dielectric materials and conventional deposition techniques keeps the intermediary approach compatible with existing processes, limiting the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protection layer effectively inhibits crack formation and propagation, enhancing the reliability and performance of the integrated circuits by maintaining structural integrity during dicing and integration processes.
Implementation Method 1
A conformal protection layer is formed over the sidewalls of semiconductor chips using atomic layer deposition
Implementation Method 2
gap filling with dielectric materials to prevent crack initiation and propagation, using processes like chemical vapor deposition
Implementation Method 3
gap filling with dielectric materials to prevent crack initiation and propagation, using processes like chemical vapor deposition and chemical mechanical polishing
Data Source
AI summary
A system-on-chip structure includes a substrate, first and second die disposed over a surface of the substrate and separated by an inter-die gap, a protection layer disposed over a sidewall of each of the first and second die, and a gap fill layer disposed over the protection layers and substantially filling the inter-die gap.