Inter-die NOC Communication Bypassing Intermediate Nodes
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Solution Overview
Problem
High latency and reduced bandwidth in data communication between programmable logic devices due to data traversing unnecessary portions of integrated circuit devices, which hampers the efficiency of operations in applications like machine learning and video processing.
Innovation Solution
Utilization of networks-on-chips (NOCs) to facilitate direct data transfer between programmable logic devices, employing communication packets that specify the source, destination, and routing nodes within the NOCs to bypass unnecessary devices and enhance inter-die communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data traverses through multiple portions and devices for communication between programmable logic devices, then communication coverage is improved, but latency increases and bandwidth decreases
Solution Approach 1:
The patent extracts and removes intermediate programmable logic devices from the data transmission path. By using direct die-to-die communication pathways, the system eliminates unnecessary intermediary devices that data would otherwise have to traverse, thereby reducing latency while maintaining communication coverage through alternative direct routes.
Solution Approach 2:
The patent introduces a new dimension of communication by implementing inter-die direct connections that bypass the traditional intra-die routing path. This dimensional shift from within-die traversal to between-die direct communication allows data to reach its destination faster without sacrificing reliability.
2Reliability
If data traverses through multiple portions and devices for communication between programmable logic devices, then communication coverage is improved, but bandwidth decreases
Solution Approach 1:
The patent removes intermediate devices from the communication path, eliminating bandwidth consumption at each intermediary stop. Direct die-to-die communication establishes a dedicated high-bandwidth pathway that bypasses the bandwidth limitations and contention inherent in multi-hop routing through multiple programmable logic devices.
Solution Approach 2:
By transitioning from intra-die to inter-die direct communication, the patent creates a parallel dimension for data flow that offers higher bandwidth capacity. This dimensional change enables more efficient data transmission volumes without compromising the ability to reach various destinations in the system.
3Speed
If direct inter-die communication is implemented using NOCs and communication packets, then latency is reduced and bandwidth is increased, but device complexity increases
Solution Approach 1:
The patent employs universally applicable Network-on-Chip (NOC) infrastructure and standardized communication packets that can handle multiple communication scenarios. This multi-functional approach allows the same complex infrastructure to serve various communication needs, justifying the increased device complexity by providing versatile, high-speed data transmission capabilities across different applications and configurations.
Solution Approach 2:
The patent introduces NOCs and communication packets as intermediary structures that manage the complexity of direct inter-die communication. These intermediaries provide standardized protocols and routing mechanisms that simplify the interaction between devices, making the complex direct communication pathway manageable and controllable while maintaining high speed and bandwidth performance.
Data Source
AI summary
An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.