Inter-Die Passive Component Assembly for Higher Circuit Density
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Solution Overview
Problem
Conventional semiconductor device assemblies with stacked dies are suboptimal for producing compact devices due to inefficiencies in interconnects and circuit component placement, leading to increased device size and reduced circuit density.
Innovation Solution
The solution involves stacking semiconductor dies with dielectric layers containing conductive material to form passive circuit components through metal-metal bonds, allowing for efficient electrical coupling and compact device assembly by embedding circuit components between the dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging processes are used to electrically couple bond pads to external terminals, then electrical connectivity is achieved, but device size increases and circuit density decreases
Solution Approach 1:
The patent transitions from planar interconnect routing to three-dimensional vertical stacking, where multiple semiconductor dies are stacked and interconnected through vertical vias and inter-die connection structures. This dimensional change allows electrical connectivity to be achieved through the thickness of the device rather than across its surface, significantly reducing the horizontal footprint and increasing circuit density while maintaining reliable electrical connections between bond pads and external terminals
Solution Approach 2:
The patent implements nested interconnect structures where conductive vias are formed within dielectric layers, and subsequent metallization layers are deposited around and within these vias. Multiple interconnect levels are nested within each other, with inner vias surrounded by dielectric material and outer metallization layers, creating a compact three-dimensional interconnect architecture that achieves electrical connectivity without increasing device footprint
2Adaptability or versatility
If circuit components are placed on die substrates, then circuit functionality is achieved, but space efficiency decreases and device size increases
Solution Approach 1:
The patent relocates circuit components from two-dimensional placement on die substrates to three-dimensional structures formed within dielectric layers between stacked dies. Passive components such as capacitors and inductors are constructed using vertical vias and inter-die connection structures, utilizing the vertical dimension and inter-die spaces to accommodate circuit functionality without consuming additional horizontal die area, thereby significantly improving space efficiency
Solution Approach 2:
The patent merges the functions of interconnect structures and passive circuit components by forming the same conductive vias and metallization layers to serve both as electrical interconnections between dies and as functional elements of passive components. This integration eliminates the need for separate dedicated spaces for interconnects and circuit components, maximizing space efficiency while maintaining full circuit functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of a compact, well-connected semiconductor device with increased circuit density by relocating circuit components to the dielectric layers between the dies, optimizing space usage and enhancing device performance.
Implementation Method 1
A metal-metal bond is formed between the first portion of the conductive material and the second portion of the conductive material to create the passive circuit component
Data Source
AI summary
A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first layer of dielectric material at which a first portion of conductive material implementing a first portion of a passive circuit component is at least partially disposed. The second semiconductor die includes a second layer of dielectric material at which a second portion of conductive material implementing a second portion of the passive circuit component is at least partially disposed. A first contact pad at the first layer of dielectric material and a second contact pad at a second layer of dielectric material are coupled to create an interconnect electrically coupling the first semiconductor die and the second semiconductor die. A metal-metal bond is formed between the first portion of the passive circuit component and the second portion of the passive circuit component to create the passive circuit component.