Inter-Die Divided Quad Clocking for 3D Stacked Memory Signal Integrity
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Solution Overview
Problem
As memory devices transition to higher clock speeds and increased stack heights, transmitting clock frequency becomes difficult and unreliable due to capacitance, resistance, and inductance on inter-die lines, leading to signal integrity issues in three-dimensional stacked memory devices.
Innovation Solution
Dividing the clock frequency in the primary memory die and transmitting a divided clock to internal memory dies via inter-die interconnects, further dividing into multiple clocks for improved signal integrity, and reconstructing the clock at the destination, which reduces power consumption and current usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to achieve higher speed memory operations, then the memory operation speed is improved, but the signal integrity deteriorates due to capacitance, resistance, and inductance on inter-die lines
Solution Approach 1:
The clock signal transmission path is segmented into multiple stages: the original clock signal is divided into multiple lower-frequency clock signals (e.g., divided by 2, 4, or 8) before transmission through inter-die lines. This segmentation reduces the frequency content that causes signal integrity issues while maintaining the ability to achieve high-speed operations through coordinated operation of multiple dies
Solution Approach 2:
The clock frequency parameter is changed from a single high frequency to multiple lower frequencies for transmission. By transmitting divided clock signals at lower frequencies (e.g., 1/2, 1/4, or 1/8 of the original clock frequency), the patent reduces the impact of capacitance, resistance, and inductance on signal integrity while still enabling high-speed memory operations through the coordinated use of multiple clock phases
2Quantity of substance
If the stack height is increased to achieve higher memory density, then the memory density is improved, but the clock signal transmission reliability deteriorates due to longer inter-die lines
Solution Approach 1:
The clock distribution system is segmented across multiple dies in the stack, with each die receiving and processing divided clock signals. This allows the memory stack to achieve high density through increased stack height while maintaining reliable clock signal transmission by using lower-frequency divided clocks that are less susceptible to degradation over the longer inter-die lines
Solution Approach 2:
The patent transitions from a single-die architecture to a three-dimensional stacked architecture, adding the vertical dimension to achieve higher memory density. By combining this dimensional change with clock signal division, the system maintains reliable clock transmission across multiple dies in the stack, overcoming the limitations of longer inter-die lines in high-density configurations
3Reliability
If the clock frequency is divided into multiple lower frequencies for transmission, then the signal integrity is improved, but the device complexity increases due to additional division circuitry
Solution Approach 1:
The divided clock signals serve multiple functions: they provide timing references for multiple memory dies, enable high-speed operations through coordinated multi-phase operation, and maintain signal integrity through lower transmission frequencies. This multi-functionality justifies the additional division circuitry by providing multiple benefits beyond simple clock generation
Data Source
AI summary
A memory device includes a clock input configured to receive a clock from a host device. The memory device also includes a command input configured to receive command and address bits from the host device. The memory device further includes multiple die stacked in a three-dimensional stack. A first die of the plurality of die includes a first plurality of memory cells and first local control circuitry. The first local circuitry includes division circuitry configured to receive the clock from the clock input, generate a divided clock having a lower frequency than that of the clock, and generate multiple clocks from the divided clock with each of the multiple clocks having a lower frequency than the divided clock. The memory device also includes one or more transmitters configured to transmit the multiple clocks using a inter-die interconnects between the multiple die.