Inter-Domain Permissions Table for Scalable Cross-Address-Space Data Movement

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Solution Overview

Problem

Existing solutions for cross-address-space data movement in computing systems face scalability challenges due to the need for O(N^2) connections between address spaces, leading to increased hardware and software complexity and performance overhead.

Innovation Solution

Implementing a single Inter-Domain Permissions Table (IDPT) entry that allows multiple submitters to access a target address space using an access control bitmap, reducing the number of required entries to O(N) and enabling scalable access control checks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If O(N^2) connections between address spaces are implemented, then cross-address-space data movement capability is improved, but hardware and software complexity increases

Engineering Contradiction:
Improvecross-address-space data movement capabilityVSAvoidhardware and software complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple IDPT entries that would traditionally be required for N submitters into a single shared IDPT entry. This entry uses an access control bitmap to manage permissions for multiple submitters simultaneously, reducing the number of IDPT entries from O(N^2) to O(N) and thereby reducing hardware and software complexity while maintaining cross-address-space data movement capability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes a single IDPT entry universal by enabling it to serve multiple submitters through the access control bitmap mechanism. The bitmap allows the same IDPT entry to be shared by N different submitters, each with their own permission bits, thus providing multi-functionality to a single entry and reducing overall system complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If O(N^2) IDPT entries are created, then access control coverage is improved, but memory consumption increases

Engineering Contradiction:
Improveaccess control coverageVSAvoidmemory consumption
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines multiple IDPT entries into a single shared entry that uses an access control bitmap to manage permissions for multiple submitters. This merging reduces memory consumption by eliminating redundant IDPT entries while the bitmap ensures that access control coverage is maintained for all N submitters through bit-level permission management

Inventive Principle:
Principle #5Merging (Combining)

3Measurement precision

If multiple IDPT entries are used for each address space pair, then access control precision is improved, but processing overhead increases

Engineering Contradiction:
Improveaccess control precisionVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent makes a single IDPT entry universal by enabling it to handle multiple submitters through the access control bitmap. This reduces processing overhead by eliminating the need to search through multiple IDPT entries, as the bitmap provides direct bit-level access control verification for each submitter, maintaining precision while improving efficiency

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12455701B2Scalable access control checking for cross-address-space data movement
Publication Date: 2025.10.28 INTEL CORP
  • US12455701B2 patent drawing
  • US12455701B2 patent drawing
  • US12455701B2 patent drawing

AI summary

Methods and apparatus relating to scalable access control checking for cross-address-space data movement are described. In an embodiment, a memory stores an Inter-Domain Permissions Table (IDPT) having a plurality of entries. At least one entry of the IDPT provides a relationship between a target address space identifier and a plurality of requester address space identifiers. A hardware accelerator device allows access to a target address space, corresponding to the target address space identifier, by one or more of requesters, corresponding to the plurality of requester address space identifiers, respectively, based at least in part on the relationship provided by the at least one entry of the IDPT. Other embodiments are also disclosed and claimed.