Inter-Execution Unit Instruction Issue Processor Design
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional processor architectures limit interaction between execution units, leading to increased power consumption, longer program execution times, and reduced performance due to the need for additional instructions to transfer data and status, as well as restricted functionality support by coprocessors.
Innovation Solution
The processor design includes execution units that can directly access and issue instructions to each other, allowing for inter-execution unit interaction without dedicated data movement instructions, enabling improved performance and reduced power consumption by allowing execution units to access necessary functionality and registers directly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If execution units are isolated with dedicated data movement instructions, then hardware complexity is reduced, but processor performance decreases and power consumption increases
Solution Approach 1:
The patent merges the instruction issue functionality into the execution units themselves, allowing execution units to directly issue instructions to each other without going through the traditional instruction fetch and decode path. This merging of functions enables direct inter-execution unit communication, improving performance while managing hardware complexity through functional integration rather than adding separate communication pathways.
Solution Approach 2:
Execution units are designed with multi-functionality, serving both as instruction executors and instruction issuers. The ability of execution units to directly issue instructions to other execution units creates a universal interface that eliminates the need for dedicated data movement instructions, thereby improving performance without proportionally increasing hardware complexity.
2Reliability
If additional instructions are used for data transfer between execution units, then reliability is improved, but program execution time increases
Solution Approach 1:
The patent extracts the data transfer function from the traditional instruction stream and embeds it directly within the execution units. By taking out the need for separate data movement instructions and integrating communication capabilities into the execution units themselves, the system maintains reliable data transfer while eliminating the time overhead of additional instructions.
Solution Approach 2:
The execution units themselves act as intermediaries for data and instruction transfer between each other. Instead of using the traditional mediator (instruction fetch/decode pathway), execution units directly communicate with each other, reducing the number of intermediate steps and thus the execution time while maintaining transfer reliability through direct controlled communication.
3Adaptability or versatility
If coprocessors have restricted functionality, then device complexity is reduced, but adaptability decreases
Solution Approach 1:
The patent introduces dynamic functionality to coprocessors through the inter-execution unit instruction issue mechanism. Execution units can dynamically issue instructions to coprocessors based on runtime requirements, allowing coprocessors to adapt to different functional needs without being statically configured with all possible functionalities. This dynamic approach increases adaptability while keeping individual coprocessor designs relatively simple.
Data Source
AI summary
A processor includes an instruction storage memory, a processor core, and an instruction merge unit. The processor core includes a plurality of execution units coupled to the instruction storage memory. A first of the execution units is configured to execute instructions provided from the instruction storage memory via a first instruction path, and to execute instructions provided by a second of the execution units via a second instruction path. The second of the execution units is configured to execute instructions provided from the instruction storage memory, and to provide instructions for execution to the first of the execution units via the second instruction path. The instruction merge unit is configured to merge the instructions provided via the first and second instruction paths into a stream of instructions to be executed by the first execution unit.