Inter-FPGA Routing Using Slack Budgeting and XDR Discretization
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Solution Overview
Problem
The delay in circuit designs emulated on field programmable gate arrays (FPGAs) is dominated by the time-multiplexing process, which is linearly proportional to the number of inter-FPGA signals, exceeding the capacity of physical connections and affecting the efficiency of the emulation process.
Innovation Solution
A method involving slack budgeting and discretization is employed to optimize the routing of electronic signals between FPGAs, using a binary-search-based discretizer to determine wire XDR and guide the routing process, while mitigating negative slack without affecting compile time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If time-multiplexing is used to send multiple inter-FPGA signals through the same physical connection, then the number of inter-FPGA signals that can be communicated is increased, but the delay of the TMX process increases linearly with the multiplexing data ratio
Solution Approach 1:
The patent applies parameter changes by adjusting the multiplexing data ratio (XDR) values assigned to different timing paths. The routing process modifies XDR parameters to balance the multiplexing load, reducing the dominant delay effect while maintaining the ability to communicate multiple signals through shared physical connections between FPGAs
2Quantity of substance
If the multiplexing data ratio (XDR) is increased to communicate more inter-FPGA signals, then the capacity of the connection is increased, but the delay of the timing path is dominated by the TMX connection delay
Solution Approach 1:
The patent applies local quality by assigning different XDR values to different timing paths based on their specific delay requirements. The routing process analyzes each timing path individually and assigns appropriate multiplexing ratios to balance the trade-off between signal capacity and timing reliability for each specific path
3Manufacturing precision
If slack budget is proportioned to timing paths based on desired delay, then the routing process is guided with desired delays, but the solution space for routing is constrained
Solution Approach 1:
The patent applies segmentation by dividing the total slack budget into proportional portions for different timing paths based on their desired delays. This segmented approach allows the routing process to handle each timing path independently with appropriate delay constraints while maintaining overall system timing requirements
Data Source
AI summary
A method includes receiving a physical circuit design file that includes physical circuit partitions that are each mapped to a respective chip. The physical circuit partitions are connected to one another by a respective timing path having an original delay. The method further includes determining a slack budget of the respective timing path, and determining a delay upper bound value based on a shortest timing path delay and the slack budget. Further, the method includes updating the delay upper bound of the respective timing path based on the slack budget, assigning an interconnection delay upper bound to a physical interconnection between at least two chips based on the updated slack budget of the respective timing path, determining a multiplexing data ratio (XDR) based on at least the interconnection delay upper bound of the physical interconnection, and performing routing between the at least two chips based on the XDR.