Inter-Gate Contacts in Stacked FETs for Further Device Scaling
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Solution Overview
Problem
There is a continued desire for further scaling and reducing the size of field-effect transistors (FETs) beyond current techniques such as fin-shaped channels and stacked nanosheet channels, particularly for next-generation stacked FET devices.
Innovation Solution
The formation of inter-gate contacts between stacked FETs, including conductive contacts disposed between and contacting the surfaces of gate regions in stacked transistors, utilizing dielectric and metal placeholders or self-aligned contact cap layers, to facilitate efficient connection and reduce device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FET scaling techniques (fin-shaped channels, stacked nanosheet channels) are used, then device performance is maintained, but device size reduction is limited
Solution Approach 1:
The patent transitions from planar FET structures to three-dimensional stacked FET configurations, stacking multiple FETs vertically to achieve further size reduction while maintaining performance through improved gate control in the vertical dimension
Solution Approach 2:
The patent divides the gate structure into multiple discrete gate regions (first gate region, second gate region) that can be independently controlled, allowing each segment to optimize performance while contributing to overall device miniaturization
2Area of stationary object
If stacked FET structures are formed without inter-gate contacts, then device complexity is reduced, but device area footprint cannot be optimized
Solution Approach 1:
The patent combines multiple FET structures into a stacked configuration sharing common substrates and support structures, reducing overall device footprint while the inter-gate contacts provide necessary electrical connections between stacked layers
Solution Approach 2:
The patent introduces dielectric layers and conductive contact structures as intermediary elements between stacked gate regions, enabling electrical connection while maintaining structural integrity and electrical isolation where needed
Data Source
AI summary
A semiconductor device comprises a first transistor comprising a first gate region, and a second transistor comprising a second gate region, wherein the second transistor is stacked over the first transistor. A conductive contact is disposed between and contacts a surface of the first gate region and a surface of the second gate region, wherein the surface of the second gate region is disposed opposite the surface of the first gate region.