Inter-level dielectric layer with hole-sealing for RC delay reduction
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Solution Overview
Problem
Advanced semiconductor technologies face challenges in reducing parasitic capacitance and RC delay due to the limitations of porous low-k dielectric materials, which are prone to delamination, cracking, and changes in dielectric constant, affecting the stability and reliability of integrated circuits.
Innovation Solution
A method involving the formation of non-penetrating holes in a dielectric layer, filled with either a porous low-k dielectric material or hole-sealing dielectric layers made of non-porous materials with a low dielectric constant, to create an inter-level dielectric layer that reduces parasitic capacitance and is easier to integrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If porous low-k dielectric materials are used to reduce parasitic capacitance, then the dielectric constant is reduced and circuit speed is improved, but the materials suffer from delamination, cohesive cracking, and diffusion issues that compromise reliability
Solution Approach 1:
The dielectric layer is segmented into multiple regions: a first dielectric layer with lower dielectric constant and a second dielectric layer with higher dielectric constant. This segmentation allows each layer to perform its specialized function - the first layer reduces parasitic capacitance while the second layer provides mechanical support and prevents delamination and cracking
Solution Approach 2:
Different regions of the dielectric structure are assigned different dielectric constants based on local requirements. The region requiring electrical performance optimization uses low-k material, while regions requiring mechanical stability use higher-k materials, achieving local optimization of both electrical and mechanical properties
2Object-generated harmful factors
If porous low-k dielectric materials with more than 20% holes are used to reduce parasitic capacitance, then the dielectric constant is reduced, but the holes cause materials to diffuse into them during polishing and metal deposition, leading to changes in dielectric constant and shorts between wires
Solution Approach 1:
A planarization layer is introduced as an intermediary between the porous low-k dielectric layer and subsequent processing layers. This planarization layer fills the holes and provides a flat surface, preventing polishing and metal deposition materials from penetrating into the porous structure, thereby maintaining control over dielectric constant and preventing wire shorts
3Stability of the object's composition
If non-porous dielectric materials are used to improve mechanical stability, then delamination and cracking are reduced, but the dielectric constant is higher which increases parasitic capacitance and RC delay
Solution Approach 1:
The dielectric structure is divided into functional segments where the first dielectric layer (lower-k) is positioned to minimize its interaction with conductors for RC delay reduction, while the second dielectric layer (higher-k) provides mechanical stability. This segmentation allows simultaneous optimization of both electrical performance and mechanical properties
Data Source
AI summary
The present invention discloses an inter-level dielectric layer for a semiconductor device, a method for manufacturing the same and a semiconductor device having said inter-level dielectric layer. The method lies in forming non-interconnected holes within a dielectric layer, and these holes may be filled with porous low-k dielectric material with a much lower dielectric constant, or forming holes within the dielectric layer by filling the upper parts of the holes. The inter-level dielectric layer in such a structure has a much lower dielectric constant, reduces RC delay between devices of integrated circuits and also is easy to integrate; besides, since the holes within the dielectric layer are non-interconnected, they shall not cause change to the dielectric constant of the dielectric material or a short circuit between wires, thus the device shall have better stability and reliability which then improve performance of the circuit.