Inter-Packet Interval Prediction for Network Processor Cache Preloading

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Solution Overview

Problem

Current network processors face challenges in reducing packet processing time, which affects data throughput, especially as throughput requirements increase, due to the delay incurred in reading packet flow data from external memory before processing can begin.

Innovation Solution

An inter-packet interval prediction algorithm with a learning phase that generates an application protocol estimation table and an inter-packet interval prediction table, allowing for the estimation of the application protocol and prediction of packet arrival times, enabling packet flow data to be preloaded in cache memory before arrival, thus reducing processing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If packet flow data is read from external memory before processing, then packet processing can begin, but processing time is delayed

Engineering Contradiction:
Improvepacket processing throughputVSAvoidpacket processing time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by predicting the arrival time of the next packet and preloading its flow data from external memory into cache memory before the packet actually arrives. This is achieved by: (1) estimating the inter-packet interval based on historical data, (2) calculating the predicted arrival time of the next packet, and (3) initiating data retrieval in advance. This eliminates the waiting time that would otherwise occur while data is being loaded from external memory.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If deep packet inspection is performed to determine application protocol, then accurate protocol identification is achieved, but processing time increases

Engineering Contradiction:
Improveapplication protocol identification accuracyVSAvoidpacket processing time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary protocol identification by using the Application Protocol Estimation Table to determine the application protocol before deep packet inspection is required. The table is populated during a learning phase where packet characteristics are analyzed, and during normal operation, the table provides rapid protocol estimation without requiring time-consuming deep inspection of packet contents.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a simplified model (copy) of packet flow patterns by storing historical packet arrival times and inter-packet intervals in the Application Protocol Estimation Table. This table serves as a pre-computed reference that allows rapid protocol identification without repeatedly performing complex analysis of actual packet data, effectively replacing deep inspection with a lookup of pre-analyzed patterns.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS9344384B2Inter-packet interval prediction operating algorithm
Publication Date: 2016.05.17 NETRONOME SYSTEMS INC
  • US9344384B2 patent drawing
  • US9344384B2 patent drawing
  • US9344384B2 patent drawing

AI summary

An appliance receives packets that are part of a flow pair, each packet sharing an application protocol. The appliance determines an estimated application protocol of the packets without performing deep packet inspection on any packets. The estimated application protocol may be determined by using an application protocol estimation table. The appliance then predicts the inter-packet interval between a packet previously received by the appliance and a next packet not yet received by the appliance. The inter-packet interval may be determined by using an inter-packet interval prediction table. The appliance then preloads packet flow data in a cache before the next packet is predicted to arrive at the appliance. Upon receiving the next packet, the packet flow data is preloaded in the cache. This reduces packet processing time by removing waiting periods previously required to cache packet flow data from an external memory after receiving the next packet.