Inter-Partition Wear Leveling in Non-Volatile Memory

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Solution Overview

Problem

Existing memory devices face disparities in write cycles across different partitions, leading to reduced lifetime due to independent wear leveling within each partition, which cannot effectively address inter-partition disparities and is restricted by read while write (RWW) limitations.

Innovation Solution

Implementing inter-partition wear leveling methods that involve a spare physical partition for swapping blocks across partitions, using a copy hardware accelerator to manage logical to physical address mappings, and performing background operations to maintain data accessibility and balance write cycles across all partitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If block level wear leveling is performed independently within each partition, then implementation simplicity is improved, but write cycle balance across partitions deteriorates

Engineering Contradiction:
Improveimplementation simplicityVSAvoidwrite cycle balance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The memory device is divided into multiple partitions, with each partition containing multiple blocks. The wear leveling system operates at two levels: intra-partition wear leveling manages blocks within each partition independently, while inter-partition wear leveling periodically redistributes data across partitions to balance write cycles. This segmented approach maintains implementation simplicity while progressively addressing write cycle balance across the entire device.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary intra-partition wear leveling operations continuously to maintain local balance, and schedules periodic inter-partition wear leveling operations to preemptively address inter-partition disparities before they significantly impact device lifetime. This preliminary action approach prevents write cycle imbalance from deteriorating.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If background copy operations are performed across partitions, then write cycle balance is improved, but read while write conflicts increase

Engineering Contradiction:
Improvewrite cycle balanceVSAvoidread while write conflicts
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

Inter-partition wear leveling is implemented as a periodic background operation rather than a continuous process. The system schedules these copy operations to occur at intervals when the memory device is less active, reducing the probability of RWW conflicts. When conflicts do occur, the system can pause or delay the background copy operation.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system uses an address mapping layer as an intermediary between the host and physical memory blocks. During inter-partition wear leveling, the mapping layer redirects host access requests to alternative physical locations, allowing background copy operations to proceed without blocking host reads and writes. This intermediary mechanism decouples the timing of background operations from host access patterns.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8601202B1Full chip wear leveling in memory device
Publication Date: 2013.12.03 MICRON TECHNOLOGY INC
  • US8601202B1 patent drawing
  • US8601202B1 patent drawing
  • US8601202B1 patent drawing

AI summary

Methods and systems to wear level a non-volatile memory device across partitions. In an embodiment, a memory device performs background operations to swap host addressable memory partitions with a spare memory partition outside of the host address space. In one embodiment, the background inter-partition wear leveling operations are appended to a user erase operations.