Inter-Plane Pad Layout for Compact Stacked Memory Bonding
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Solution Overview
Problem
Conventional semiconductor memory devices face signal delay issues due to the placement of pad parts at the edges of memory chips, leading to increased device size and inefficient signal transmission when stacked.
Innovation Solution
A memory device design featuring inter-plane pad parts between adjacent planes, allowing for direct bonding and flip-chip bonding of memory chips without the need for edge-based wire bonding, reducing signal transmission paths and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If pad parts are disposed at edges of memory chips for connection, then ease of manufacture is improved, but device size increases and signal delay occurs
Solution Approach 1:
The pad parts are relocated from the edge position (2D boundary) to the inter-plane position (3D internal space between stacked memory chips). This dimensional transition from 2D edge placement to 3D internal placement allows the pad parts to be positioned within the stacked structure rather than at the periphery, thereby reducing the overall device footprint while maintaining manufacturing feasibility through standard bonding processes.
2Ease of manufacture
If pad parts are disposed at edges of memory chips for connection, then ease of manufacture is improved, but signal transmission speed deteriorates
Solution Approach 1:
The relocation of pad parts to the inter-plane position creates shorter signal transmission paths by positioning the connection points closer to the memory cells in the stacked architecture. This dimensional repositioning reduces the distance signals must travel from the pad parts to the functional circuits, thereby improving signal transmission speed while still allowing for conventional manufacturing techniques.
3Ease of manufacture
If wire bonding is used for connecting stacked memory chips, then ease of manufacture is improved, but device complexity increases
Solution Approach 1:
The wire bonding process and associated structures are extracted and eliminated from the device architecture. By positioning pad parts at the inter-plane position, the invention enables direct bonding or other simplified connection methods between stacked memory chips, removing the need for complex wire bonding infrastructure and reducing overall device complexity while maintaining manufacturing capability.
4Reliability
If additional redistribution lines are added to compensate for signal delay, then signal transmission quality is improved, but device size increases
Solution Approach 1:
The inter-plane pad part positioning inherently reduces signal path length, which directly improves signal transmission quality without requiring additional compensation structures. This dimensional repositioning eliminates the need for extra redistribution lines that would otherwise be required to compensate for longer signal paths, thereby maintaining signal integrity while avoiding increased device size.
Data Source
AI summary
A memory device may include a first structure and a second structure bonded to the first structure. The first structure may have a plurality of planes and a pad part between two planes adjacent to each other among the plurality of planes. Each of the plurality of planes may include a memory cell. The second structure may include a peripheral circuit. The plurality of planes may be minimum units in which operations are independently performed and may be in an n×m array (n and m being integers of 2 or larger). The pad part may be between the rows and/or between the columns of the n×m array.