Inter-plane Pad Structure for Stacked Memory Signal Delay
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Solution Overview
Problem
Conventional semiconductor memory devices experience signal delay and increased size due to the placement of pad parts at the edges of memory chips when stacked, leading to inefficiencies in signal transmission.
Innovation Solution
The memory device incorporates an inter-plane pad structure where pad parts are positioned between planes, allowing for direct bonding and flip-chip bonding of memory chips, reducing signal transmission paths and eliminating the need for edge-based wire bonding, thereby minimizing signal delay and device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pad parts are disposed at edges of memory chips and memory chips are connected using wires, then connection between memory chips is achieved, but the size of the memory device is increased and signal delay occurs
Solution Approach 1:
The pad part is repositioned from the edge of the memory chip to the space between stacked memory chips (inter-plane region). This spatial reconfiguration in the vertical dimension eliminates the need for lateral wire extensions, reducing the device footprint while maintaining electrical connectivity between chips.
Solution Approach 2:
The pad part is nested within the inter-plane space between stacked memory chips rather than occupying edge regions. This nested configuration allows the pad to be integrated into the existing vertical stack structure, eliminating additional lateral space requirements and reducing overall device size.
2Reliability
If pad parts are disposed at edges of memory chips and memory chips are connected using wires, then connection between memory chips is achieved, but signal delay occurs due to placement of pad parts at edges
Solution Approach 1:
The pad part is repositioned from the edge of the memory chip to the space between stacked memory chips (inter-plane region). This spatial reconfiguration in the vertical dimension eliminates the need for lateral wire extensions, reducing the device footprint while maintaining electrical connectivity between chips.
Solution Approach 2:
The pad part is nested within the inter-plane space between stacked memory chips rather than occupying edge regions. This nested configuration allows the pad to be integrated into the existing vertical stack structure, eliminating additional lateral space requirements and reducing overall device size.
3Reliability
If pad parts are disposed at edges of memory chips, then connection between memory chips is achieved, but additional redistribution lines are required increasing device complexity
Solution Approach 1:
The pad part is extracted from the edge region and repositioned to the inter-plane space. This extraction eliminates the need for redistribution lines that would otherwise be required to route signals from edge pads to internal circuitry, simplifying the overall device architecture.
Solution Approach 2:
The pad part is repositioned from the edge of the memory chip to the space between stacked memory chips (inter-plane region). This spatial reconfiguration in the vertical dimension eliminates the need for lateral wire extensions, reducing the device footprint while maintaining electrical connectivity between chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces signal loading time and resistance by up to 90%, enhancing signal transmission efficiency and allowing for more compact device design without the need for additional redistribution lines or buffer circuits.
Implementation Method 1
a first structure and a second structure bonded to the first structure
Data Source
Figure 1
Figure 2
Figure 3~4b
AI summary
A memory device may include a first structure (ST1) and a second structure (ST2) bonded to the first structure (ST1). The first structure (ST1) may have a plurality of planes (PL1-PL6) and a pad part (PDP; PDP1, PDP2) between two planes adjacent to each other among the plurality of planes (PL1-PL6). Each of the plurality of planes (PL1-PL6) may include a memory cell. The second structure (ST2) may include a peripheral circuit. The plurality of planes (PL1-PL6) may be minimum units in which operations are independently performed and may be in an n x m array (n and m being integers of 2 or larger). The pad part (PDP; PDP1, PDP2) may be between the rows and/or between the columns of the n x m array.