Inter-Rank Clock Delay Tuning for Multi-Rank Memory Modules
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Solution Overview
Problem
In multi-rank semiconductor memory systems, achieving signal integrity for command/address signals is challenging due to variations in signal characteristics between ranks, leading to difficulties in maintaining optimal clock timing without reducing performance or burdening system components.
Innovation Solution
A memory module and system design that includes a first and second memory device sharing a command/address signal and clock signal, with a variable adjustment circuit in the first memory device to adjust the clock signal, and a delay control logic to set the delay based on command bus training results, allowing for matched reception of signals across ranks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If individual timing control is implemented for each rank in the memory controller, then signal integrity is improved, but device complexity and performance are reduced
Solution Approach 1:
The timing adjustment function is extracted from the memory controller and relocated to the memory devices themselves. Each memory device includes a delay control logic and variable delay logic that can independently adjust their own clock signal timing based on training results, eliminating the need for complex centralized control in the memory controller.
Solution Approach 2:
Each memory device performs self-adjustment of its clock timing through built-in delay control logic that uses training patterns to determine optimal delay values. The device autonomously configures its own timing parameters without requiring continuous external control, reducing the burden on the memory controller.
2Reliability
If separate timing control is implemented for each rank, then clock skew compensation is improved, but productivity and performance are reduced
Solution Approach 1:
Timing adjustment is performed in advance during a training phase before normal memory operations begin. The delay control logic determines optimal delay values using training patterns, and these settings are then applied and maintained during subsequent high-performance memory access operations, ensuring both accurate skew compensation and sustained productivity.
Solution Approach 2:
The system implements dynamic timing adjustment during the training phase, where delay values are optimized based on actual signal characteristics. Once optimized, the timing configuration is fixed to enable high-speed operations, providing adaptability when needed while maintaining stability during performance-critical operations.
3Reliability
If matched type reception is implemented for CA and clock signals, then signal integrity is improved, but manufacturing complexity increases
Solution Approach 1:
Instead of requiring precise physical matching of signal paths during manufacturing, the invention uses variable delay logic that can electronically adjust the clock signal timing parameter. This allows matched-type reception to be achieved through programmable delay adjustment rather than through complex physical layout constraints, significantly easing manufacturing requirements.
Data Source
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AI summary
There is provided a memory module (1500) including a first memory device(1200), and a second memory device (1300) configured to share a command/address signal and a clock signal with the first memory device (1200). The first memory device (1200) and the second memory device (1300) receive the command/address signal and the clock signal in a matched type, and the first memory device (1200) includes a variable delay line (1240) for adjusting a delay of the received clock signal. The first memory device (1200) may constitute a first rank (Rank0), and the second memory device (1300) may constitute a second rank (Rank1).