Inter-Sheet Filler Layer for Multi-Patterned Metal Gate Control
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Solution Overview
Problem
Existing integrated circuits face challenges in increasing computing power due to difficulties in obtaining gate electrodes with desired characteristics for nanostructure transistors, leading to issues with transistor performance and wafer yields.
Innovation Solution
The formation of an inter-sheet filler layer between semiconductor nanostructures in transistors, which is selectively removed to prevent unwanted gate metal deposition, allowing for distinct threshold voltages and robust gate dielectrics by preventing prolonged etching processes that erode the gate dielectric materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate metal is deposited to fill spaces between semiconductor nanostructures, then gate electrode characteristics are improved, but gate dielectric materials are eroded due to prolonged etching processes
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial filler layer between the semiconductor nanostructures before gate metal deposition. This filler layer is removed selectively to expose the gate dielectric only in regions where gate metal should be deposited, preventing prolonged etching exposure and protecting the gate dielectric integrity while still enabling precise gate electrode formation.
Solution Approach 2:
The patent uses a sacrificial filler layer as an intermediary element that temporarily occupies the space between semiconductor nanostructures during processing. This intermediary is selectively removed to control gate metal deposition, serving as a mediator that protects the gate dielectric from prolonged etching while enabling precise gate electrode formation in desired regions.
2Adaptability or versatility
If multiple gate metals are used to achieve distinct threshold voltages, then transistor functionality is improved, but process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the gate electrode into multiple distinct metal layers, each with different work functions. The first gate metal layer is deposited in first regions with first threshold voltages, and the second gate metal layer is deposited in second regions with second threshold voltages. This segmentation enables independent control of threshold voltages in different transistor regions while maintaining a unified fabrication process.
Solution Approach 2:
The patent implements local quality by applying different gate metal materials to different spatial regions of the substrate. First gate metal with specific properties is deposited in first regions, while second gate metal with different properties is deposited in second regions. This local differentiation enables distinct threshold voltages in different transistor regions without requiring entirely separate processing lines.
3Productivity
If semiconductor nanostructures are made smaller to increase computing power, then transistor density is improved, but difficulty in obtaining desired gate electrode characteristics increases
Solution Approach 1:
The patent replaces mechanical/physical direct filling approaches with a chemical deposition process. Instead of attempting to mechanically fill tiny spaces between increasingly small semiconductor nanostructures, the invention uses atomic layer deposition (ALD) or chemical vapor deposition (CVD) to conformally deposit gate metal and filler layers. This substitution of deposition methodology enables precise control of gate electrode characteristics even as nanostructure dimensions shrink.
Solution Approach 2:
The patent applies parameter changes by utilizing the work function properties of different metal materials. By selecting gate metals with specific work functions (first gate metal and second gate metal with different work functions), the invention can achieve distinct threshold voltages in different transistor regions. This parameter-based control allows precise tailoring of gate electrode characteristics independent of the shrinking physical dimensions of the nanostructures.
Data Source
AI summary
An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. When forming the integrated circuit, an inter-sheet fill layer is deposited between semiconductor nanostructures of the second nanostructure transistor. A first gate metal layer is deposited between semiconductor nanostructures of the first nanostructure transistor while the inter-sheet filler layer is between the semiconductor nanostructures of the second nanostructure transistor. The inter-sheet filler layer is utilized to ensure that the first gate metal is not deposited between the semiconductor nanostructures of the second nanostructure transistor.