Inter-Sheet Filler Layer for Multi-Patterned Nanostructure Gates
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Solution Overview
Problem
Existing integrated circuits face challenges in increasing computing power due to difficulties in obtaining gate electrodes with desired characteristics for nanostructure transistors, leading to issues with transistor performance and wafer yields.
Innovation Solution
The formation of an inter-sheet filler layer between semiconductor nanostructures in nanostructure transistors, which is selectively removed to prevent gate metal deposition between certain transistors, allowing for distinct threshold voltages and robust gate dielectrics, thereby improving transistor performance and wafer yields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If gate metal is deposited uniformly across all transistors, then manufacturing process is simple, but gate electrodes cannot achieve desired characteristics for different transistor types
Solution Approach 1:
The gate metal deposition process is segmented into multiple sequential steps with selective masking. Different gate metal layers (first gate metal, second gate metal) are deposited at different stages, allowing different transistor types to receive different metal combinations. This segmentation enables tailored gate electrode characteristics for each transistor type while maintaining a systematic manufacturing approach.
Solution Approach 2:
A preliminary gate dielectric layer is formed on all semiconductor nanostructures before any gate metal deposition. This preliminary dielectric layer serves as a protective foundation that prevents gate metal from contacting the semiconductor nanostructures in transistor types where such contact is undesired, enabling subsequent selective metal deposition without direct semiconductor exposure.
2Productivity
If gate metal fills gaps between all semiconductor nanostructures, then deposition is complete, but unwanted gate metal must be removed from certain transistors requiring additional processing
Solution Approach 1:
The gate dielectric layer is preliminarily deposited to cover all semiconductor nanostructures before gate metal deposition. This preliminary protective layer allows complete gate metal filling in desired transistors while automatically preventing metal contact in undesired transistors, eliminating the need for subsequent selective removal processes.
Solution Approach 2:
The gate dielectric layer acts as an intermediary between the gate metal and semiconductor nanostructures. In transistor types where gate metal contact is undesired, this intermediary layer blocks the metal, allowing complete deposition without subsequent removal. The intermediary enables single-step complete filling while achieving selective functionality.
3Reliability
If gate metal contacts semiconductor nanostructures in all transistors, then electrical connection is achieved, but threshold voltage control and dielectric integrity are compromised
Solution Approach 1:
The gate dielectric layer is applied with local quality differentiation - it serves as a protective barrier in transistor types where metal contact is undesired, while allowing metal contact in transistor types where electrical connection is required. This spatially varying function of the dielectric layer enables both dielectric integrity protection and electrical connection where needed.
Solution Approach 2:
The gate dielectric layer is preliminarily formed to establish protective coverage before any gate metal deposition occurs. This preliminary protective action ensures that in transistor types requiring dielectric integrity, the metal cannot contact the semiconductor nanostructures, while in other types the metal can penetrate or contact through designated pathways.
Data Source
AI summary
An integrated circuit includes a first nanostructure transistor and a second nanostructure transistor. When forming the integrated circuit, an inter-sheet fill layer is deposited between semiconductor nanostructures of the second nanostructure transistor. A first gate metal layer is deposited between semiconductor nanostructures of the first nanostructure transistor while the inter-sheet filler layer is between the semiconductor nanostructures of the second nanostructure transistor. The inter-sheet filler layer is utilized to ensure that the first gate metal is not deposited between the semiconductor nanostructures of the second nanostructure transistor.