Inter-thread Communication via Cache Coherence Messages
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Solution Overview
Problem
Traditional shared memory communication in multi-threaded systems is wasteful of system resources, particularly bus bandwidth, due to the need for threads to repeatedly read shared memory locations to detect changes, which leads to unnecessary cache coherence messages being broadcast across the system bus.
Innovation Solution
Threads can use cache coherence messages to detect changes in shared memory locations without reading the new value, allowing them to enter an infinite or effectively infinite loop and receive indications of modifications via cache coherence messages, thereby reducing the need for superfluous bus operations and improving resource efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a receiving thread repeatedly reads a shared memory location to detect changes, then the thread can reliably detect when a sending thread modifies the value, but this causes wasteful consumption of system bus bandwidth due to unnecessary cache coherence messages
Solution Approach 1:
The patent extracts the change detection mechanism from the shared memory read operation itself. Instead of detecting changes through repeated reads, the system uses separate cache coherence messages (such as invalidate messages in MESI protocol) that are naturally generated during memory modification operations to notify receiving threads of changes. This separates the detection function from the data transfer function, allowing reliable change detection without requiring receiving threads to repeatedly read shared memory and generate unnecessary coherence traffic.
2Speed
If a receiving thread spins in an infinite loop waiting for a shared memory location to change, then the thread can respond immediately when a change occurs, but this wastes processor time and prevents the thread from yielding to other threads
Solution Approach 1:
The patent implements feedback through cache coherence messages that provide real-time notification to receiving threads when shared memory locations are modified. When a sending thread writes to a shared memory location, the cache coherence protocol automatically generates invalidate or update messages that are sent to processors holding cached copies of that location. This feedback mechanism allows receiving threads to be notified immediately of changes without continuously polling, enabling immediate response while allowing the thread to yield the processor to other threads during the waiting period.
3Measurement precision
If a receiving thread reads a shared memory location twice to detect modifications, then the thread can confirm that a change has occurred, but this causes the processor to broadcast at least two cache coherence messages across the system bus
Solution Approach 1:
The patent applies preliminary action by having the sending thread generate cache coherence messages (such as invalidate messages) at the time of the memory write operation, before the receiving thread needs to detect the change. This preliminary notification ensures that when the receiving thread subsequently reads the shared memory location, it can do so with the knowledge that coherence messages have already been broadcast, eliminating the need for a second read and second coherence message broadcast to confirm the change.
Data Source
AI summary
In shared-memory computer systems, threads may communicate with one another using shared memory. A receiving thread may poll a message target location repeatedly to detect the delivery of a message. Such polling may cause excessive cache coherency traffic and/or congestion on various system buses and/or other interconnects. A method for inter-processor communication may reduce such bus traffic by reducing the number of reads performed and/or the number of cache coherency messages necessary to pass messages. The method may include a thread reading the value of a message target location once, and determining that this value has been modified by detecting inter-processor messages, such as cache coherence messages, indicative of such modification. In systems that support transactional memory, a thread may use transactional memory primitives to detect the cache coherence messages. This may be done by starting a transaction, reading the target memory location, and spinning until the transaction is aborted.