Inter-Tier PDN Layout for Dense 3D Logic Power and Heat Management
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Solution Overview
Problem
Conventional two-dimensional semiconductor fabrication faces scaling challenges as transistors are packed more densely, necessitating a transition to three-dimensional integration to increase transistor density without adequate power delivery and heat management solutions.
Innovation Solution
A multi-tier semiconductor structure with inter-tier power delivery networks (PDN) and through-silicon vias (TSV) for efficient power distribution and heat management, allowing for vertical stacking of logic and memory cells with dense connectivity, while shielding lower tiers from high-temperature processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are stacked vertically in 3D integration to increase transistor density, then transistor density is improved, but power delivery and heat management become more difficult
Solution Approach 1:
The patent transitions from conventional 2D power delivery networks to a 3D inter-tier PDN architecture where power and ground planes are stacked vertically across multiple semiconductor tiers. This dimensional change enables direct vertical power delivery through TSVs, reducing current path length and improving power delivery efficiency while managing heat dissipation in the vertical dimension.
Solution Approach 2:
The patent implements nested PDN structures where primary and secondary power delivery networks are hierarchically organized across tiers. The primary PDN provides bulk power delivery while secondary PDN structures provide local power distribution, creating a nested architecture that efficiently manages power at multiple scales simultaneously.
2Power
If primary PDN structure is disposed over lower semiconductor device tier, then power delivery to upper tier is improved, but lower tier becomes exposed to high-temperature processing
Solution Approach 1:
The patent introduces a secondary PDN structure as an intermediary layer between the primary PDN and the lower semiconductor device tier. This secondary structure acts as a thermal barrier that shields the lower tier from high-temperature processing during fabrication while maintaining electrical connectivity through TSVs, thus resolving the conflict between power delivery efficiency and thermal protection.
3Reliability
If TSV structure penetrates primary PDN structure, then vertical electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent forms TSVs through the primary PDN structure at an early fabrication stage before final assembly, enabling preliminary establishment of vertical electrical connectivity pathways. This preliminary action simplifies subsequent assembly processes by pre-configuring the inter-tier connection infrastructure.
Data Source
AI summary
Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.