Inter-Tier Vias for 3D-IC Routing Flexibility
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Solution Overview
Problem
Conventional 3D-ICs face inefficiencies in silicon area utilization for electrical routing between stacked dies, leading to suboptimal layout and routing flexibility.
Innovation Solution
The implementation of inter-tier vias and dummy gates allows for efficient electrical interconnections between microelectronic components on top and bottom tiers of 3D-ICs, utilizing floating gates as conduction layers without increasing layout area and enhancing routing flexibility by connecting metal layers across tiers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional 3D-IC packaging is used, then three-dimensional integration is achieved, but layout area is not fully optimized and routing flexibility is insufficient
Solution Approach 1:
The patent introduces inter-tier vias that extend vertically through the substrate, enabling electrical connections in the third dimension (z-axis) between metal layers on different tiers. This dimensional transition allows routing to escape the constraints of planar 2D layout, providing flexible inter-tier connectivity without increasing the chip's footprint area.
Solution Approach 2:
The patent divides the circuit into multiple tiers (first tier and second tier) stacked vertically, with each tier containing separate metal layers. This segmentation allows independent optimization of routing on each tier while using inter-tier vias to connect corresponding metal layers, thereby improving overall routing flexibility without sacrificing area efficiency.
2Adaptability or versatility
If more metal layers are added for routing, then routing flexibility improves, but layout area increases
Solution Approach 1:
Instead of adding more metal layers in the planar direction (x-y plane), the patent utilizes the vertical dimension (z-axis) by forming inter-tier vias through the substrate. This allows connection between metal layers on different tiers without expanding the chip's lateral footprint, effectively increasing routing resources while maintaining area efficiency.
Solution Approach 2:
The patent implements a nested structure where multiple metal layers are stacked vertically on different tiers, with inter-tier vias providing vertical access between corresponding layers. This nesting approach maximizes the use of vertical space for routing, allowing dense interconnection without increasing the chip's planar area.
3Adaptability or versatility
If inter-tier vias are implemented, then routing flexibility and area efficiency improve, but manufacturing complexity increases
Solution Approach 1:
The patent forms inter-tier vias and fills them with conductive material before completing the metal layer formation on the second tier. This preliminary action ensures that the via structures are already in place and ready for connection, simplifying subsequent processing steps and reducing overall manufacturing complexity despite the added functionality.
Solution Approach 2:
The inter-tier vias serve multiple functions: they provide electrical connection between metal layers on different tiers, act as alignment references for subsequent processing, and enable flexible routing paths. This multi-functionality reduces the need for additional dedicated structures, thereby managing manufacturing complexity while achieving routing flexibility.
Data Source
AI summary
A 3D-IC includes a first tier device and a second tier device. The first tier device and the second tier device are vertically stacked together. The first tier device includes a first substrate and a first interconnect structure formed over the first substrate. The second tier device includes a second substrate, a doped region formed in the second substrate, a dummy gate formed over the substrate, and a second interconnect structure formed over the second substrate. The 3D-IC also includes an inter-tier via extends vertically through the second substrate. The inter-tier via has a first end and a second end opposite the first end. The first end of the inter-tier via is coupled to the first interconnect structure. The second end of the inter-tier via is coupled to one of: the doped region, the dummy gate, or the second interconnect structure.