Inter-Track Coherence Circuitry for Magnetic Storage

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current data storage technologies face challenges in maintaining inter-track coherence between adjacent tracks in magnetic storage media, leading to timing and processing errors due to variations in spindle speed and media characteristics, which complicates the write process and reduces data storage density.

Innovation Solution

An assembly and method that determine inter-track coherence using phase and frequency offsets from timing recovery circuitry, processed by coherence circuitry to align signals from multiple read elements, employing a transfer function to calculate initial inter-track phase and frequency offsets and account for skew angle, thereby synchronizing data across tracks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If decreased track width is used to increase areal storage densities, then storage density is improved, but inter-track coherence deteriorates

Engineering Contradiction:

Improveareal storage densityVSAvoidinter-track coherence

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The system uses timing recovery circuitry to continuously monitor phase and frequency offsets between adjacent tracks and feeds this information back to coherence circuitry, which then adjusts processing parameters to maintain coherence despite track width reductions

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The invention dynamically changes processing parameters including phase offset correction and frequency offset adjustment based on measured coherence conditions, allowing the system to adapt to varying inter-track coherence caused by spindle speed variations and media characteristics

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If spindle speed varies, then data storage flexibility is improved, but timing accuracy deteriorates

Engineering Contradiction:

Improvespindle speed flexibilityVSAvoidtiming accuracy

Core Design Contradiction:

Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Timing recovery circuitry continuously measures phase and frequency offsets from timing signals and feeds this information to coherence circuitry, which adjusts timing parameters in real-time to compensate for spindle speed variations and maintain accurate data timing

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts timing recovery and coherence parameters based on real-time conditions rather than using fixed settings, allowing it to adapt to varying spindle speeds while maintaining timing accuracy through continuous parameter optimization

Inventive Principle:

Principle #15Dynamics

3Productivity

If multiple read elements are used to read adjacent tracks, then data reading capability is improved, but signal processing complexity deteriorates

Engineering Contradiction:

Improvedata reading capabilityVSAvoidsignal processing complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The signal processing function is divided into separate dedicated circuitry modules: timing recovery circuitry that handles phase and frequency offset measurement for each track, and coherence circuitry that processes the coherence determination, which simplifies the overall processing of multiple track signals

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8786970B2Determining inter-track coherence using output signals from first and second tracks

Publication Date: 2014.07.22 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD

AI summary

An assembly and method to determine adjacent track coherence is disclosed. The assembly includes coherence circuitry configured to receive phase and frequency offsets from timing recovery circuitry and determine an inter-track phase and frequency coherence between the encoded data on a first track and the encoded data on a second track adjacent to the first track utilizing the frequency and phase offsets from the timing recovery circuitry for the output signals corresponding to the first and second tracks.