Inter-VM Interrupt Handling via Posted Descriptors

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Solution Overview

Problem

Current virtualization systems incur overhead due to VM exits when sending interrupts between virtual machines, which can lead to inefficiencies in communication and resource management.

Innovation Solution

The implementation of an inter-VM-IPI instruction that allows notifications or interrupts to be sent between virtual machines without causing a VM exit, using a processor with virtualization extensions and a posted-interrupt descriptor format to manage interrupts efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional interrupt handling between virtual machines is used, then interrupts can be sent between VMs, but VM exits are triggered causing overhead and inefficiency

Engineering Contradiction:
Improveinterrupt handling efficiencyVSAvoidtime lost due to VM exits
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent introduces a posted interrupt descriptor as an intermediary data structure that enables interrupt notification between VMs without triggering VM exits. The descriptor contains interrupt information and is posted to a memory location accessible by the target VM, allowing the interrupt to be handled directly by the guest OS without hypervisor involvement.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the interrupt notification mechanism from the traditional VM exit path. By using posted interrupt descriptors that are directly accessible to guest VMs, the interrupt handling is separated from the hypervisor control flow, eliminating the need for VM exits while maintaining interrupt delivery functionality.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If VM exits are used for inter-VM communication, then interrupts can be delivered between VMs, but system overhead increases

Engineering Contradiction:
Improveinterrupt delivery reliabilityVSAvoidsystem complexity due to hypervisor involvement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent enables VMs to self-service interrupt handling by posting interrupt descriptors to memory locations that are directly accessible to the target VM. The guest OS can autonomously process these interrupts without requiring hypervisor mediation, reducing system complexity while maintaining reliable interrupt delivery.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent prepares interrupt descriptors in advance and posts them to predetermined memory locations before the interrupt needs to be handled. This preliminary action allows the target VM to immediately process the interrupt when it occurs, eliminating the need for complex runtime hypervisor intervention.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If traditional interrupt mechanisms are used, then interrupts can be handled, but resource management efficiency decreases

Engineering Contradiction:
Improveinterrupt handling simplicityVSAvoidresource management efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent replaces the mechanical VM exit mechanism with a memory-based posted interrupt descriptor system. This substitution eliminates the overhead of context switching and hypervisor intervention, improving resource management efficiency while maintaining the simplicity of interrupt handling through standardized descriptor formats.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10713195B2Interrupts between virtual machines
Publication Date: 2020.07.14 INTEL CORP
  • US10713195B2 patent drawing
  • US10713195B2 patent drawing
  • US10713195B2 patent drawing

AI summary

Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.