User-Interactive Application Pipelining with Managed Buffers
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Solution Overview
Problem
Existing computing systems face inefficiencies in processing large volumes of data for pipelined and dataflow computing applications, leading to longer processing latencies due to serial execution of stages and suboptimal utilization of hardware resources.
Innovation Solution
Implementing a buffer-pipelined application system (BPAS) that utilizes pipeline buffers to enable interactive pipelining of execution stages, allowing concurrent processing of data batches through a buffer-pipeline manager (BPM) to allocate resources efficiently among physical memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If serial execution of processing stages is used, then device complexity is reduced, but processing latency increases and productivity decreases
Solution Approach 1:
The patent segments the processing application into multiple independent stages that can execute in parallel. Each stage is assigned to different processing elements and operates on different portions of the input data simultaneously, thereby reducing overall processing latency without requiring complex inter-stage coordination hardware.
Solution Approach 2:
The patent implements preliminary action by pre-allocating buffer memory regions for each processing stage before execution begins. Input data is pre-loaded into input buffers, and output buffers are pre-configured to receive results, eliminating runtime memory management overhead and reducing execution latency.
2Speed
If parallel execution of processing stages is implemented, then processing speed increases, but resource utilization becomes suboptimal
Solution Approach 1:
The patent ensures continuity of useful action by implementing a buffering system that maintains continuous data flow between processing stages. While one stage is processing data, other stages simultaneously process different data portions, and completed results are immediately transferred to output buffers, preventing idle processing elements and maximizing resource utilization.
Solution Approach 2:
The patent introduces buffer memory as an intermediary between processing stages. These buffers decouple the execution of different stages, allowing each stage to operate independently at its own pace while maintaining overall system throughput, thereby improving both speed and resource utilization simultaneously.
3Loss of time
If buffer pipelining is implemented, then processing latency is reduced, but device complexity increases
Solution Approach 1:
The patent implements a universal buffer management approach where a single buffer pool serves multiple processing stages. The same buffer memory regions are dynamically allocated and deallocated for different stages throughout execution, eliminating the need for dedicated buffers for each stage and reducing overall system complexity while maintaining low latency.
Data Source
AI summary
A method of pipelining execution stages of a pipelined application can comprise a Buffer Pipeline Manager (BPM) of a Buffer Pipelined Application computing System (BPAS) allocating pipeline buffers, configuring access to the pipeline buffers by stage processors of the system, transferring buffers from one stage processor to a successor stage processor, and transferring data from a buffer in one memory to a buffer in an alternative memory. The BPM can allocate the buffers based on execution parameters associated with the pipelined application and/or stage processors. The BPM can transfer data to a buffer in an alternative memory based on performance, capacity, and/or topological attributes of the memories and/or processors utilizing the memories. The BPM can perform operations of the method responsive to interfaces of a Pipeline Programming Interface (PPI). A BPAS can comprise hardware processors, physical memories, stage processors, an application execution program, the PPI, and the BPM.