Interactive NoC Topology Editing for SoC Design
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Solution Overview
Problem
Existing network-on-chip (NoC) design tools require restarting and re-execution of synthesis processes for minor changes, leading to inconsistent results and reduced usability for SoC designers due to the nature of constraint solver approaches, which fail to ensure complete and correct connectivity in NoC topologies.
Innovation Solution
A tool that guides designers through interactive topology editing sessions by allowing the creation and modification of NoC topologies, ensuring desired connectivity and adherence to rules through user-defined inputs and automatic updates, with features like insertion, deletion, and replacement of elements, while reporting rule violations and allowing for step-by-step corrections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the synthesis tool is restarted and re-executed for every change to NoC topology or constraints, then the tool can generate a new NoC configuration, but the results may be completely different each time leading to inconsistency and reduced usability
Solution Approach 1:
The system performs preliminary actions by maintaining the current best-known NoC configuration and using it as a starting point for subsequent synthesis iterations. Instead of starting from scratch each time, the system pre-pops the synthesis tool with the existing configuration, enabling incremental refinement while maintaining consistency across design iterations.
Solution Approach 2:
The system implements feedback by continuously monitoring synthesis results and comparing them against the current best-known configuration. When improvements are detected, the system feeds back these enhanced configurations to update the baseline, ensuring that each iteration builds upon proven successful designs rather than generating inconsistent random solutions.
2Adaptability or versatility
If the synthesis tool is restarted for minor changes, then updated constraints can be processed, but all previous logic synthesis and place-and-route work must be redone from scratch
Solution Approach 1:
The system performs preliminary action by maintaining and preserving the current best-known NoC configuration throughout the design process. This configuration serves as a reusable foundation that can be incrementally updated without requiring complete re-synthesis, thereby preserving previous design work and reducing redundant computation time.
Solution Approach 2:
The system applies discarding and recovering by selectively discarding only the specific constraint changes while recovering and reusing the proven effective portions of the existing NoC configuration. This allows the system to maintain valuable design work while adapting to new requirements, avoiding the need to discard and redo all previous work.
3Productivity
If the constraint solver uses a traditional approach to minimize metrics, then optimization can be achieved, but the solver may find very different solutions in response to minor changes
Solution Approach 1:
The system performs preliminary action by pre-populating the synthesis tool with the current best-known configuration before each synthesis run. This provides a stable starting point that guides the constraint solver toward consistent optimization paths, reducing the variability of solutions while maintaining metric optimization through incremental improvements.
Solution Approach 2:
The system implements feedback by continuously comparing synthesis results against the best-known configuration and selectively adopting improvements. This feedback mechanism ensures that optimization proceeds in a controlled, consistent manner, maintaining solution stability while still achieving metric minimization through cumulative refinements.
Data Source
AI summary
A system and method implemented by tool is disclosed. The tool receives input of a network-on-chip (NoC) and the NoC's desired connectivity and efficiently guides the designer through interactive NoC topology editing sessions to ensure the obtained network is both complete and correct during topology creation or modification.