Interactive Software-to-Hardware Compilation for Formal Verification
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Solution Overview
Problem
Formal verification systems face limitations in handling large or complex software and hardware combinations, leading to computational complexity and increased costs, as they struggle to perform verification on integrated systems effectively.
Innovation Solution
Implementing interactive compilation of software into a hardware language to satisfy formal verification constraints, where the software is translated into a hardware language, allowing for joint verification with the hardware design, and using a compiler with features like lexical analysis, syntax tree generation, and constraint evaluation to identify and address potential issues, thereby reducing the size and complexity of the code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software and hardware are verified separately using formal verification systems, then verification can be performed on each component individually, but integration flaws between hardware and software may remain undetected
Solution Approach 1:
The patent combines hardware and software verification into a single integrated formal verification process. The system translates software code into hardware description language and performs joint verification of hardware-software interactions, enabling detection of integration flaws that would be missed in separate verification processes.
Solution Approach 2:
The patent introduces an intermediate representation layer that translates software code into hardware description language. This intermediary translation layer enables the formal verification system to process both hardware and software components uniformly, facilitating integrated verification while managing complexity through standardized transformation rules.
2Reliability
If formal verification is performed on large or complex hardware-software combinations, then comprehensive verification coverage can be achieved, but computational complexity increases significantly
Solution Approach 1:
The patent segments the verification process into distinct phases: software-to-hardware translation, constraint generation, and formal verification. This segmentation allows the system to handle large hardware-software combinations by processing them in manageable stages, reducing peak computational requirements while maintaining comprehensive verification coverage.
Solution Approach 2:
The patent performs preliminary translation of software code into hardware description language and pre-generates verification constraints before the actual formal verification process. This preliminary action prepares the verification inputs in advance, reducing the computational burden during the main verification phase and enabling efficient handling of complex systems.
3Reliability
If software code is translated into hardware language for formal verification, then integrated verification can be performed, but the translation process adds complexity to the compilation workflow
Solution Approach 1:
The patent implements a universal translation framework that converts software code into hardware description language using standardized intermediate representations. This universal approach enables the same compilation infrastructure to handle multiple software-to-hardware translation scenarios, reducing overall system complexity despite the added translation capability.
Data Source
AI summary
Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.