Inter-Chip Qubit Controller for Delay-Aware Cross-Resonance Readout

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Solution Overview

Problem

In quantum computers with qubits placed on different chips, optimizing control and readout timings for cross-resonance coupling is challenging due to increased transmission delays, leading to decreased readout accuracy and prolonged computation times.

Innovation Solution

A controller with a control circuit, read circuit, and adjustment circuit is employed to adjust the control and readout timings based on measured delays between qubits, optimizing these timings to improve accuracy and reduce computation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If qubits for cross-resonance coupling are placed on different chips, then device scalability is improved, but transmission delay increases

Engineering Contradiction:
Improvedevice scalabilityVSAvoidtransmission delay
Core Design Contradiction:
Volume of moving objectVSLoss of time

Solution Approach 1:

The quantum computing system is divided into multiple chips, each containing qubits that can be independently manufactured and tested. This segmentation allows for scalable device construction while the controller compensates for inter-chip transmission delays through timing adjustment

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller dynamically adjusts the timing parameters of control signals and readout operations based on the specific transmission delays between qubits on different chips. By changing the temporal parameters of operations, the system optimizes performance despite variable transmission delays

Inventive Principle:
Principle #35Parameter changes

2Volume of moving object

If transmission delay between qubits on different chips increases, then device scalability is improved, but readout accuracy deteriorates

Engineering Contradiction:
Improvedevice scalabilityVSAvoidreadout accuracy
Core Design Contradiction:
Volume of moving objectVSMeasurement precision

Solution Approach 1:

The system measures the actual transmission delays between qubits and uses this feedback information to adjust control and readout timings. This closed-loop approach ensures that readout accuracy is maintained despite variations in transmission delay caused by different chip configurations

Inventive Principle:
Principle #23Feedback

3Device complexity

If fixed control and readout timings are used, then device complexity is reduced, but computation time increases

Engineering Contradiction:
Improvedevice complexityVSAvoidcomputation time
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The controller implements dynamic timing adjustment for control signals and readout operations based on measured transmission delays. This dynamic approach replaces fixed timings with adaptive timing that optimizes computation speed while maintaining manageable device complexity through automated adjustment

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The controller enhances readout accuracy and reduces computational time by dynamically adjusting control and readout timings, effectively handling increased delays in qubits placed on different chips.

Implementation Method 1

a cross-resonance gate that couples a plurality of qubits

Methodology Applied
Scientific EffectCross-resonance coupling: Resonance

Data Source

PatentEP4697242A1Controller, information processing apparatus and method
Publication Date: 2026.02.18 FUJITSU LTD
  • EP4697242A1 patent drawingFigure 1
  • EP4697242A1 patent drawingFigure 2
  • EP4697242A1 patent drawingFigure 3

AI summary

A controller includes a control circuit configured to output a control signal to cause cross-resonance between a plurality of qubits that are placed on different chips, to one of the plurality of qubits, a read circuit configured to output readout signals for performing readout from the plurality of qubits to the respective qubits; and an adjustment circuit configured to adjust an interval between an output of the control signal and outputs of the readout signals based on a delay between the plurality of qubits.