Inter-Chip Temporal Redundancy for Fault-Tolerant 3D Links
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Solution Overview
Problem
In 3D chip stacks, existing solutions for interconnect failures are inflexible and inefficient, as they require pre-determined spare channels that consume valuable silicon resources and do not effectively utilize spare transmission capacity.
Innovation Solution
Implementing temporal redundancy by steering data bits to functional channels operating at a higher clock rate when a fault occurs, allowing for fault tolerance without additional physical spare channels, thereby utilizing spare transmission capacity in the time domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spare interconnect channels are provided to replace faulty channels, then fault tolerance is improved, but silicon real estate and routing resources are consumed
Solution Approach 1:
The patent transitions from spatial redundancy (adding more physical channels in space) to temporal redundancy (using existing channels at different time rates). By operating functional channels at higher clock rates, the system provides fault tolerance without consuming additional silicon real estate, effectively moving the redundancy solution from the spatial dimension to the temporal dimension.
Solution Approach 2:
The patent changes the operational parameter of clock rate for functional channels. When a fault is detected, the system increases the clock rate of remaining functional channels to compensate for the lost capacity. This parameter change allows the system to maintain fault tolerance while utilizing existing physical resources more efficiently.
2Reliability
If pre-determined spare channels are provided, then fault tolerance is improved, but flexibility is reduced
Solution Approach 1:
The patent implements a dynamic fault tolerance mechanism where the system continuously monitors channel health and adapts its operation in real-time. When faults are detected, the system dynamically reconfigures by steering data to functional channels and adjusting clock rates, providing flexibility that pre-determined static spare channels cannot achieve.
Solution Approach 2:
The system performs self-diagnosis and self-reconfiguration when faults occur. The fault detection and steering logic automatically identifies failed channels and redirects traffic without external intervention, making the system adaptable to various fault scenarios without requiring pre-configured spare channels for every possible failure mode.
3Reliability
If data bits are reassigned to functional channels at higher clock rates, then fault tolerance is improved, but transmission complexity increases
Solution Approach 1:
The patent introduces steering logic as an intermediary component that manages the reassignment of data bits between channels. This intermediary element simplifies the complexity by providing a centralized control mechanism that handles channel selection and clock rate adjustment, rather than requiring complex distributed control across all channels.
Data Source
AI summary
A circuit is provided to facilitate temporal redundancy for inter-chip communication. When an inter-chip communication channel fails, data bits associated with the faulty channel are steered to a non-faulty channel and transmitted via the non-faulty channel together with data bits associated with the non-faulty channel at an increased data rate.