Interconnect Structure With 2D Liners for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor device dimensions decrease, the challenge of reduced capacitance coupling and increased parasitic capacitance due to smaller spacings between conductive features in integrated circuits necessitates innovative solutions to maintain performance and functionality.
Innovation Solution
The implementation of a two-dimensional material liner and selectively formed dielectric layers in the interconnection structure, which prevent dielectric material deposition on conductive features and reduce capacitance coupling by controlling thickness and etch selectivity, thereby minimizing line-to-line leakage and overlay shift issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor device dimensions are reduced to increase density, then device functionality and performance are improved, but capacitance coupling between conductive features increases and parasitic capacitance increases
Solution Approach 1:
A two-dimensional material liner is introduced as an intermediary layer between dielectric materials and conductive features. This liner prevents direct interaction between the dielectric material and conductive feature surfaces, thereby reducing parasitic capacitance and line-to-line leakage while enabling closer spacing of conductive features for higher density.
Solution Approach 2:
The two-dimensional material liner is selectively formed only on specific conductive features (e.g., first conductive features) rather than uniformly on all conductive features. This local application optimizes the balance between reducing capacitance coupling where needed and maintaining electrical performance where direct dielectric contact is beneficial.
2Productivity
If spacing between conductive features is reduced to increase density, then device functionality is improved, but line-to-line leakage increases
Solution Approach 1:
The two-dimensional material liner acts as a mediator that prevents direct electrical interaction between adjacent conductive features through the dielectric material. By blocking charge transfer pathways at the conductive feature surfaces, the liner reduces line-to-line leakage even when features are closely spaced.
Solution Approach 2:
The introduction of the two-dimensional material liner changes the electrical parameters at the dielectric-conductive feature interface. The liner modifies surface properties and electrical characteristics, enabling reduced leakage currents while maintaining the geometric configuration needed for high density.
3Object-generated harmful factors
If two-dimensional material liner is formed on conductive features to reduce capacitance coupling, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The two-dimensional material liner is selectively formed only on specific conductive features rather than uniformly on all conductive features. This selective approach reduces parasitic capacitance at critical interfaces while avoiding unnecessary complexity in regions where direct dielectric contact is acceptable or beneficial.
Solution Approach 2:
The manufacturing process utilizes self-aligned formation methods where the two-dimensional material liner is deposited conformally on conductive features and subsequently patterned using the same lithographic alignment references. This self-service approach minimizes additional alignment steps and reduces overall process complexity despite the added structural element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance coupling and line-to-line leakage, enhancing the reliability and performance of semiconductor devices by controlling dielectric material deposition and etch processes, thus maintaining device integrity and functionality at smaller scales.
Implementation Method 1
selectively formed dielectric layers in the interconnection structure, which prevent dielectric material deposition on conductive features
Implementation Method 2
controlling thickness and etch selectivity, thereby minimizing line-to-line leakage
Data Source
AI summary
An interconnection structure, along with methods of forming such, are described. The structure includes a first conductive feature, a first liner having a first top surface disposed on the first conductive feature, a second conductive feature disposed adjacent the first conductive feature, and a second liner disposed on at least a portion of the second conductive feature. The second liner has a second top surface, and the first liner and the second liner each comprises a two-dimensional material. The structure further includes a first dielectric material disposed between the first and second conductive features and a dielectric layer disposed on the first dielectric material. The dielectric layer has a third top surface, and the first, second, and third top surfaces are substantially co-planar.