Interconnect Adhesion Layer Structure for Delamination Resistance

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Solution Overview

Problem

As semiconductor technology advances, the scaling down of integrated circuit (IC) geometries leads to challenges such as increased stress and delamination risks in interconnect structures due to the complexity and miniaturization of components, which affects production efficiency and reliability.

Innovation Solution

The implementation of an adhesion layer with a non-conformal structure and a conductive feature with a footing portion, which reduces stress and sharp corners during etching processes, thereby protecting layers and preventing delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If conventional interconnect structures are used in scaled-down semiconductor devices, then manufacturing processes can be simplified, but stress and delamination risks increase due to miniaturization

Engineering Contradiction:

Improveinterconnect structure complexityVSAvoiddelamination resistance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The adhesion layer is divided into two distinct portions: a first portion with greater thickness disposed on the conductive feature, and a second portion with greater width disposed on the dielectric layer. This segmentation allows each portion to fulfill specific functions - the thicker first portion provides enhanced adhesion to the conductive feature, while the wider second portion distributes stress across the dielectric layer, preventing delamination without requiring complex overall structure

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the adhesion layer are given different properties - the first portion has greater thickness for strong bonding to the conductive feature, while the second portion has greater width for stress distribution on the dielectric layer. This local differentiation of properties allows the single adhesion layer to address multiple concerns (adhesion strength and stress management) without increasing overall structural complexity

Inventive Principle:

Principle #3Local quality

2Productivity

If geometry scaling is continued to increase production efficiency, then manufacturing costs decrease, but stress concentration and sharp corners in interconnect structures increase

Engineering Contradiction:

Improveproduction efficiencyVSAvoidstress concentration

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The conductive feature is designed with a footing portion that has a curved or rounded geometry instead of sharp corners. This curvature distributes stress more evenly across the structure, eliminating stress concentration points that would otherwise form at sharp corners during etching and fabrication processes, thereby maintaining reliability even as overall device dimensions are scaled down

Inventive Principle:

Principle #14Spheroidality (Curvature)

3Reliability

If adhesion layer thickness is increased uniformly to prevent delamination, then delamination resistance improves, but manufacturing precision and stress distribution worsen

Engineering Contradiction:

Improvedelamination resistanceVSAvoidlayer thickness control

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

Rather than uniformly increasing the adhesion layer thickness throughout, the layer is segmented into two portions with different dimensions. The first portion has greater thickness for adhesion to the conductive feature, while the second portion has greater width for stress distribution on the dielectric layer. This segmentation allows precise control of each portion's function without requiring uniform thickness increases that would compromise manufacturing precision

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The adhesion layer parameters (thickness and width) are changed in different regions rather than uniformly. The first portion has increased thickness parameter, while the second portion has increased width parameter. This localized parameter change allows optimization of adhesion and stress distribution functions independently, maintaining manufacturing precision while improving delamination resistance

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20230411279A1Semiconductor device structure and methods of forming the same

Publication Date: 2023.12.21 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device structure, along with methods of forming such, are described. The structure includes an interconnect structure disposed over a substrate, a first conductive feature disposed in the interconnect structure, a dielectric layer disposed on the interconnect structure, and a second conductive feature having a top portion and a bottom portion. The top portion is disposed over the dielectric layer, and the bottom portion is disposed through the dielectric layer. The structure further includes an adhesion layer disposed over the dielectric layer and the second conductive feature. The adhesion layer includes a first portion disposed on a top of the second conductive feature and a second portion disposed over the dielectric layer, the first portion has a thickness, and the second portion has a width substantially greater than the thickness.