Interconnect Air-Gap Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
The increasing parasitic capacitance between metal interconnects in high-density integrated circuits, such as VLSI circuits, leads to RC delay and cross-talk, necessitating improved interconnect structures for advanced semiconductor manufacturing.
Innovation Solution
Incorporation of air gaps between conductive features in interconnect structures, formed by selective deposition of inhibitor caps on conductive features followed by deposition of dielectric material to seal the gaps, reduces coupling capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If low-k dielectric materials are employed to form ILD and IMD layers, then parasitic capacitance is reduced, but manufacturing complexity increases due to additional process steps
Solution Approach 1:
The patent divides the dielectric layer formation into multiple segments: first forming a mandrel layer, then depositing a dielectric material layer, and finally creating air gaps between interconnect lines. This segmented approach allows for precise control of capacitance reduction while managing manufacturing complexity through systematic process breakdown
Solution Approach 2:
The patent introduces an intermediary mandrel layer that facilitates the formation of air gaps. This mandrel structure serves as a temporary scaffold during manufacturing, enabling controlled dielectric deposition and subsequent air gap formation without requiring complex direct patterning processes
2Productivity
If feature sizes are shrunk to increase integration density, then device functionality is enhanced, but parasitic capacitance and RC delay increase
Solution Approach 1:
The patent applies local quality modification by creating air gaps specifically in the regions between interconnect lines where capacitance is most problematic. The dielectric material is selectively deposited and removed to form air gaps only in critical areas, maintaining low capacitance locally while preserving overall high integration density
Solution Approach 2:
The patent changes the physical parameters of the dielectric structure by introducing air gaps with near-zero dielectric constant, fundamentally altering the capacitance parameter. This parameter change allows continued scaling of feature sizes without proportional increase in RC delay, as the air gap regions provide capacitance isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces coupling capacitance, improving device performance by minimizing RC delay and enhancing reliability through reduced leakage and electromigration.
Implementation Method 1
selective deposition of inhibitor caps on conductive features that are removed after a subsequent deposition of dielectric material
Implementation Method 2
The inhibitor cap is removed with a plasma treatment
Implementation Method 3
deposition of dielectric material to seal the gaps
Data Source
AI summary
A semiconductor device includes a first conductive feature, a first dielectric layer over the first conductive feature, a second conductive feature extending through the first dielectric layer, an air gap between the first dielectric layer and the second conductive feature, and an etch stop layer over the second conductive feature and the first dielectric layer. The etch stop layer covers the air gap, and the air gap extends above a bottommost surface of the etch stop layer.