Stacked Interconnect Air Gap RC Delay Reduction
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Solution Overview
Problem
Current silicon CMOS technology faces challenges in maintaining low RC time delay as metal lines shrink, increasing resistance and capacitance, which are not adequately addressed by even low dielectric-constant materials like ultra-low k porous SiCOH, necessitating further reduction in RC values to comply with the International Technology Roadmap for Semiconductors and Moore's law.
Innovation Solution
The introduction of air gaps between conductive layers in interconnect structures, achieved through a method involving the formation of sacrificial layers and etching processes, reduces effective dielectric constant and RC time constant by replacing insulating layers with air, enabling efficient RC propagation delays for future technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If metal lines are shrunk to scale technology nodes, then device density is improved, but resistance increases and RC time delay worsens
Solution Approach 1:
The patent employs porous low-k dielectric materials (such as SiCOH with dielectric constant of 2.4) to replace conventional dielectric materials. The porous structure reduces the effective dielectric constant, thereby lowering capacitance between adjacent metal lines and reducing RC time delay while maintaining scaled dimensions
Solution Approach 2:
The patent uses composite material structures combining copper metal lines with porous SiCOH dielectric layers. This composite approach leverages the high conductivity of copper to minimize resistance and the low dielectric constant of porous SiCOH to minimize capacitance, collectively addressing the RC time delay challenge in scaled technologies
2Volume of moving object
If inter-metal dielectric layers are thinned to increase device density, then area is improved, but capacitance increases and RC time delay worsens
Solution Approach 1:
The patent introduces porous low-k dielectric materials with controlled porosity to reduce the effective dielectric constant. By maintaining air voids within the dielectric structure, capacitance between closely spaced metal lines is reduced, allowing thinner dielectric layers without increasing RC time delay
Solution Approach 2:
The patent modifies the dielectric constant parameter of the inter-metal dielectric layer by transitioning from conventional materials to porous low-k materials. This parameter change enables thinner dielectric layers to be used while maintaining low capacitance values, thus supporting higher device density without worsening RC performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the effective dielectric constant from 2.4 to 1.2, resulting in a 40% to 50% decrease in RC time constant, effectively meeting the demands of smaller technology nodes and supporting next-generation semiconductor technologies.
Implementation Method 1
performing an etch to remove the sacrificial material layer through the via and leave a resultant air gap between the first conductive layer and the second conductive layer
Implementation Method 2
increase the effective dielectric constant between the first and second conductive layers
Data Source
AI summary
A stacked interconnect structure includes a first conductive layer, a second conductive layer, and a first dielectric layer disposed between the first and second conductive layers and having an air gap in a portion of the first dielectric layer that separates the first and second conductive layers. A second dielectric layer is parallel to the first conductive layer, a third dielectric layer overlays a portion of the second dielectric layer and contacts two opposing surfaces of the second conductive layer. A first via extends into the air gap of the first dielectric layer, wherein the second conductive layer is separated from the first via by a portion of the third dielectric layer that extends from a given surface of the third dielectric layer to the second dielectric layer, and a second via that extends from the given surface of the third dielectric layer to the second conductive layer.