Interconnect Air-Gap Sealing Structure for RC Delay Reduction

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Solution Overview

Problem

The reduction in dimensions of interconnecting structures in integrated circuits leads to increased resistance and parasitic capacitance, causing RC delay effects, and the use of air gaps is limited by small sizes and structural collapse risks due to insufficient mechanical support from low-k dielectric materials.

Innovation Solution

A semiconductor structure is formed with a silicon layer partially sealing air gaps between interconnecting structures, using a sputtering deposition process to create a silicon oxide layer that seals the gaps and a low-k dielectric layer for additional support, reducing parasitic capacitance and structural collapse risks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If air gaps are introduced between interconnecting structures to reduce parasitic capacitance, then RC delay is reduced, but the risk of structural collapse increases due to insufficient mechanical support from low-k dielectric materials

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidstructural stability
Core Design Contradiction:
Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent uses a composite structure combining low-k dielectric material and silicon oxide material. The low-k dielectric material fills the air gap to reduce parasitic capacitance, while the silicon oxide material provides mechanical support to prevent structural collapse. This composite approach allows both capacitive reduction and structural stability to be achieved simultaneously.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The silicon oxide material acts as an intermediary between the low-k dielectric material and the surrounding structures. It provides the necessary mechanical strength and support to the low-k material, which otherwise would be too soft to maintain structural integrity. The intermediary silicon oxide layer enables the low-k material to perform its capacitive reduction function without causing structural collapse.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If the sizes of air gaps are increased to effectively reduce parasitic capacitance, then RC delay reduction improves, but the risk of structural collapse increases due to insufficient mechanical supporting

Engineering Contradiction:
Improveparasitic capacitanceVSAvoidmechanical support
Core Design Contradiction:
Object-generated harmful factorsVSStrength

Solution Approach 1:

The patent creates a composite filling structure where low-k dielectric material and silicon oxide material work together. The low-k material is placed in the air gap to reduce parasitic capacitance, while the silicon oxide material provides the mechanical strength needed to support larger air gap dimensions without causing structural collapse.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies different materials with different properties to different regions: low-k dielectric material is used where capacitance reduction is needed (in the air gap region), while silicon oxide material is used where mechanical support is needed (providing structural reinforcement). This local differentiation of material properties allows both电容 reduction and mechanical support to be optimized in their respective regions.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces parasitic capacitance and RC delay while enhancing structural support, allowing for larger air gaps and improved performance in integrated circuits.

Implementation Method 1

performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer and at least partially sealing an air gap in the trench

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS11804403B2Semiconductor structure and method for forming the same
Publication Date: 2023.10.31 UNITED SEMICONDUCTOR (XIAMEN) CO LTD
  • US11804403B2 patent drawing
  • US11804403B2 patent drawing
  • US11804403B2 patent drawing

AI summary

A semiconductor structure and a method for forming the same are disclosed. The method includes the steps of forming a first dielectric layer on a substrate, forming a plurality of first interconnecting structures in the first dielectric layer, forming at least a trench in the first dielectric layer and between the first interconnecting structures, performing a sputtering deposition process to form a second dielectric layer on the first dielectric layer, wherein the second dielectric layer at least partially seals an air gap in the trench, and forming a third dielectric layer on the second dielectric layer.