Interconnect Structures with Air Gaps for Low Parasitic Capacitance
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving higher packing densities and smaller device sizes due to limitations in multilayer interconnection structures, particularly in forming reliable and efficient interconnections with low parasitic capacitance.
Innovation Solution
A manufacturing method involving sequential formation of conductive and dielectric layers, etching processes, and the use of dummy materials and adhesion layers to create via holes and trenches, followed by filling with conductive material and forming air gaps to reduce parasitic capacitance and enhance electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multilayer interconnection structures are used to increase packing density, then device functional density is improved, but parasitic capacitance increases and electrical performance deteriorates
Solution Approach 1:
The patent introduces air gaps (porous structures) between adjacent conductive interconnections. These air gaps have significantly lower dielectric constant compared to traditional dielectric materials, thereby reducing parasitic capacitance between neighboring interconnections while maintaining the multilayer high-density interconnection structure.
Solution Approach 2:
The patent segments the dielectric material by creating air gaps that divide and isolate adjacent conductive interconnections. This segmentation reduces the electromagnetic coupling between neighboring interconnections, thereby reducing parasitic capacitance while preserving the overall multilayer interconnection density.
2Productivity
If feature size is reduced to increase functional density, then device size is improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent forms a mandrel structure before creating the final interconnection geometry. This preliminary structure serves as a template that guides subsequent etching and material deposition processes, ensuring precise formation of via holes and trenches even at reduced feature sizes. The mandrel approach pre-defines the geometric parameters, making the manufacturing process more controllable and precise.
Solution Approach 2:
The mandrel acts as an intermediary structure during manufacturing. It is formed first, then used to define the geometry of the final interconnection structures through etching. This intermediary approach simplifies the direct patterning process and improves manufacturing precision by using a sacrificial structure that can be formed with higher precision than the final fine-pitch features.
3Ease of manufacture
If conventional etching processes are used, then manufacturing simplicity is maintained, but process window for tuning is limited and yield is reduced
Solution Approach 1:
The patent forms a mandrel structure with specific geometric parameters (width, depth, profile) before the final etching process. This preliminary structure allows tuning of the process window by adjusting mandrel dimensions and etch conditions, providing greater control over the final interconnection geometry while maintaining manufacturing simplicity. The mandrel serves as a tunable parameter that can be optimized independently of the final feature dimensions.
Data Source
AI summary
A method for manufacturing an interconnect structure is provided, and the method is as below. A dielectric layer is deposited over a substrate. The dielectric layer is etched to form a recess. A dummy adhesion layer is deposited on sidewalls of the recess. A conductive layer is formed in the recess. The dummy adhesion layer is removed to expose a portion of the conductive layer.