Interconnect Annealing for Electromigration and Copper Oxide Control
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Solution Overview
Problem
Existing semiconductor back-end of line (BEOL) processes face challenges in addressing electromigration, particularly due to the formation of voids and impurities like copper oxide, while conventional annealing methods require lengthy processing times and suboptimal temperatures that hinder grain growth and device performance.
Innovation Solution
A method involving a high-temperature, short-time annealing process (400-450°C for 5 minutes or less) with a hydrogen and nitrogen atmosphere is applied to the top surface of a conductor, accompanied by a trench formation and deposition of a barrier layer, followed by polishing, to enhance grain growth and remove impurities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional annealing process is used with lower temperature (300°C) to avoid affecting front-end devices, then device performance is preserved, but grain growth is limited and processing time is lengthy
Solution Approach 1:
The patent changes the annealing temperature parameter from conventional 300°C to a higher range of 400-450°C, enabling sufficient grain growth and impurity removal while maintaining short processing time (5 minutes or less). This parameter change resolves the contradiction by allowing higher temperature to achieve better metallurgical quality without requiring extended duration that would affect front-end devices.
Solution Approach 2:
The patent implements a periodic annealing process with specific timing (5 minutes or less) and temperature cycling (400-450°C), creating an optimized thermal profile that achieves grain growth and impurity removal in a controlled, time-limited manner, thus resolving the time-temperature tradeoff.
2Reliability
If conventional annealing process is used with lower temperature (300°C), then front-end device performance is protected, but electromigration reliability is insufficient due to limited grain growth
Solution Approach 1:
By changing the temperature parameter to 400-450°C range, the patent enables sufficient grain growth that reduces grain boundary density and improves electromigration resistance. This parameter change directly addresses the reliability issue by creating larger grains that are more resistant to electromigration effects.
Solution Approach 2:
The patent performs preliminary high-temperature annealing on the conductor before subsequent processing steps, establishing large grain structures and removing impurities in advance. This preliminary action ensures electromigration resistance is built into the structure before it undergoes further manufacturing steps.
3Reliability
If longer processing time is used to achieve sufficient grain growth, then electromigration resistance is improved, but front-end device performance is affected
Solution Approach 1:
The patent changes both temperature and time parameters simultaneously - using higher temperature (400-450°C) combined with shorter duration (5 minutes or less). This parameter combination achieves the necessary grain growth for electromigration resistance while limiting total thermal exposure to protect front-end devices.
Solution Approach 2:
The patent rushes through the annealing process by using high temperature for a brief period, achieving the essential grain growth and impurity removal functions quickly before thermal damage can affect front-end devices. This rushed approach skips the need for prolonged low-temperature processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces processing time, forms larger crystal grains, and effectively eliminates copper oxide, thereby improving the reliability of the interconnect structure without affecting front-end device performance.
Implementation Method 1
The top surface of the first conductor is then subjected to an anneal process with conditions including an annealing temperature of 400-450° C. for a time period of less than 5 minutes
Implementation Method 2
larger crystal grains can be formed in the metal conductor
Implementation Method 3
the impurity problem such as copper oxide in the metal conductor can be solved
Data Source
AI summary
A method for fabricating an interconnect structure is disclosed. A substrate with a first dielectric layer is provided. A first conductor is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer. A trench is formed in the second dielectric layer to expose the top surface of the first conductor. An annealing process is performed on the top surface of the first conductor. The annealing process includes the conditions of a temperature of 400-450° C., duration less than 5 minutes, and gaseous atmosphere comprising hydrogen and nitrogen.