Interconnect Bandwidth Table for Asymmetric Scheduling

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Solution Overview

Problem

Current information handling systems lack efficient scheduling algorithms that optimize interconnect link bandwidth allocation, leading to suboptimal performance due to asymmetric memory access and unaccounted bandwidth variations across interconnect links, resulting in potential saturation and reduced system efficiency.

Innovation Solution

An information handling system that calculates interconnect link bandwidth values and populates an interconnect bandwidth table (IBT) to prioritize resource allocation based on available bandwidth, allowing the operating system to schedule processes on interconnect links with maximum available bandwidth, thereby avoiding oversubscription and enhancing performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional scheduling algorithms are used without considering interconnect link bandwidth variations, then system complexity is reduced and ease of operation is maintained, but system performance deteriorates due to suboptimal resource allocation and potential interconnect link saturation

Engineering Contradiction:
Improvesystem performanceVSAvoidscheduling system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs preliminary actions by calculating and storing interconnect link bandwidth values in an interconnect bandwidth table (IBT) during system initialization or configuration phase. This pre-computed bandwidth information is then used by the scheduler to make informed decisions about process placement and resource allocation, avoiding the need for complex real-time bandwidth measurements while still achieving optimized scheduling

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interconnect bandwidth table (IBT) acts as an intermediary data structure that stores pre-calculated bandwidth values between different sockets and interconnect links. This table serves as a lookup reference for the scheduler, simplifying the scheduling decision-making process by providing ready-to-use bandwidth information without requiring complex real-time calculations or measurements

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If interconnect link bandwidth is not monitored and managed, then device complexity and operational overhead are reduced, but harmful factors increase due to interconnect link saturation and system efficiency degradation

Engineering Contradiction:
Improveinterconnect link reliabilityVSAvoidinterconnect link saturation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The system implements feedback by using the pre-calculated interconnect bandwidth values stored in the IBT to inform scheduling decisions. The scheduler continuously references this bandwidth information to allocate processes and tasks in a way that prevents interconnect link saturation, creating a feedback loop where bandwidth data directly influences resource allocation to maintain system reliability

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system takes preliminary anti-action by pre-calculating and storing interconnect bandwidth capacities before scheduling begins. This advance knowledge allows the scheduler to proactively prevent interconnect link saturation by avoiding allocations that would exceed bandwidth thresholds, rather than reacting to saturation problems after they occur

Inventive Principle:
Principle #9Preliminary anti-action

Data Source

PatentUS10990562B2System and method of asymmetric system description for optimized scheduling
Publication Date: 2021.04.27 DELL PROD LP
  • US10990562B2 patent drawing
  • US10990562B2 patent drawing
  • US10990562B2 patent drawing

AI summary

An information handling system includes processors disposed in sockets, and interconnect links providing point-to-point links between the sockets. One of the processors determines an arrangement of the processors, memories and the interconnect links, and determines a value for each of the processors, each of the memories, and each of the interconnect links. The processor calculates interconnect link bandwidth values for each of the interconnect links based at least in part on the determined value and the arrangement of the processors, the memories and the interconnect links. The processor also populates an interconnect bandwidth table using the interconnect link bandwidth values.