Interconnect Barrier Layer Layout for Low-Resistance Corrosion Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down devices due to increased device resistance and corrosion issues, particularly with the use of new materials and geometries in interconnect structures, which affect the efficiency and reliability of integrated circuits.
Innovation Solution
The implementation of interconnect structures with a barrier layer that does not cover the bottom surfaces of conductive features, combined with a treatment process to passivate the exposed surfaces, and the use of multiple liner layers that are intermixed on sidewalls to improve adhesion of the conductive fill material, reducing device resistance and corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed to cover the bottom surfaces of conductive features, then corrosion is reduced, but device resistance increases
Solution Approach 1:
The barrier layer is selectively formed only on the sidewalls of the conductive features, leaving the bottom surfaces exposed. This local application provides corrosion protection where needed (sidewalls) while avoiding resistance increase at the bottom contact areas, thus resolving the contradiction between corrosion resistance and device resistance.
2Productivity
If new materials and geometries are used to facilitate scaling down, then device density increases, but device resistance and corrosion issues worsen
Solution Approach 1:
The selective sidewall-only barrier layer formation addresses the corrosion and resistance issues that arise from new materials and geometries used in scaled-down devices, while maintaining the high device density enabled by these advanced structures.
Solution Approach 2:
The interconnect structure uses a composite approach combining different materials (copper fill, ruthenium liner, cobalt liner) with specific geometries (sidewall-only barrier), allowing the device to benefit from both the high density of scaled-down geometries and the improved electrical properties of carefully selected material combinations.
3Ease of manufacture
If multiple liner layers are formed to improve adhesion, then filling process improves, but device complexity increases
Solution Approach 1:
The liner structure is segmented into multiple functional layers (ruthenium outer liner, cobalt inner liner) with distinct roles: the ruthenium provides adhesion to the barrier layer and prevents copper diffusion, while the cobalt enhances adhesion to the copper fill material. This segmentation improves the filling process while managing complexity through clear functional differentiation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases device resistance and reduces corrosion, enhancing the efficiency and reliability of interconnect structures in semiconductor devices by improving the adhesion and filling processes within the interconnect levels.
Implementation Method 1
a treatment process to passivate the exposed surfaces
Data Source
AI summary
A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.