Interconnect Electron Barrier Layers for Leakage-Resistant Scaling

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The scaling down of semiconductor devices has resulted in smaller electrical isolation regions between adjacent conductive structures in interconnect structures, leading to electron migration and current leakage, which degrades semiconductor device performance.

Innovation Solution

The implementation of electron barrier layers with hole carrier induced electron trap sites, formed through plasma treatment with low bombardment energy plasma, to trap migrating electrons, and the use of nitride capping layers to enhance the reliability of interconnect structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the dimensions of semiconductor devices are scaled down to meet higher storage capacity and processing speed demands, then device performance and integration density are improved, but the electrical isolation regions between adjacent conductive structures become smaller, leading to electron migration and current leakage

Engineering Contradiction:
Improvestorage capacity and processing speedVSAvoidelectron migration control
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A nitrogen-rich layer is introduced as an intermediary between adjacent conductive structures to prevent electron migration. The layer acts as a mediator that captures migrating electrons through hole carriers, preventing them from reaching neighboring conductive structures and causing current leakage.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The electrical and chemical properties of the isolation region are changed by nitrogen enrichment. The nitrogen-rich layer creates a high concentration of hole carriers that fundamentally alter the region's ability to block electron migration, transforming it from a passive dielectric barrier to an active electron-trapping layer.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If conventional plasma treatment is used to form electron barrier layers, then electron migration prevention is achieved, but high bombardment energy damages the underlying conductive structures and increases manufacturing complexity

Engineering Contradiction:
Improveelectron barrier layer effectivenessVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The plasma treatment parameters are changed by using low bombardment energy conditions. This allows the plasma to enrich the dielectric layer with nitrogen without causing damage to underlying conductive structures, simplifying the manufacturing process by eliminating the need for additional protective layers or complex multi-step procedures.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The electron barrier layers and nitride capping layers significantly improve the reliability of interconnect structures by 20 to 30 times compared to structures without them, effectively preventing electron migration and reducing current leakage.

Implementation Method 1

formed through plasma treatment with low bombardment energy plasma

Methodology Applied
Scientific EffectPlasma treatment: Plasma

Implementation Method 2

to trap migrating electrons

Methodology Applied
Scientific EffectElectron trapping: Absorption (physical)

Implementation Method 3

effectively preventing electron migration and reducing current leakage

Methodology Applied
Scientific EffectElectron migration prevention: Electrical Resistance

Data Source

PatentUS12354907B2Electron migration control in interconnect structures
Publication Date: 2025.07.08 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12354907B2 patent drawing
  • US12354907B2 patent drawing
  • US12354907B2 patent drawing

AI summary

A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.