Interconnect Barrier Stack for Low-k Adhesion and Diffusion Control
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Solution Overview
Problem
As semiconductor devices become denser and circuit elements smaller, resistance-capacitance (RC) delay time significantly impacts integrated circuit performance, necessitating the use of low-k dielectric materials to reduce RC delay.
Innovation Solution
The method involves forming a semiconductor device with a specific etch stop stack and dielectric layer structure, including a Group IV element-doped layer and a low-k dielectric layer, and using a surface treatment and inhibitor portions to control the deposition of barrier layers and conductive materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are used to reduce RC delay, then circuit performance is improved, but adhesion between conductive materials and dielectric layers deteriorates
Solution Approach 1:
A barrier layer is introduced as an intermediary between the conductive material (e.g., copper) and the low-k dielectric material. This barrier layer prevents direct contact between the conductive material and the low-k dielectric, thereby preventing adhesion deterioration while maintaining the low RC delay benefit of the low-k dielectric material.
Solution Approach 2:
The barrier layer is deposited in advance before the conductive material is formed, creating a protective interface that prevents harmful adhesion interactions between the conductive material and the low-k dielectric material from occurring in the first place.
2Ease of manufacture
If conductive materials are deposited directly on dielectric layers, then manufacturing process is simplified, but metal diffusion into dielectric layers occurs
Solution Approach 1:
The barrier layer serves as a diffusion barrier, preventing metal atoms from the conductive material from diffusing into the low-k dielectric material, thereby maintaining the compositional stability of the dielectric layer while allowing the manufacturing process to remain relatively simple.
3Reliability
If etch stop layers are added to control deposition, then adhesion and diffusion control are improved, but device complexity increases
Solution Approach 1:
The barrier layer performs multiple functions simultaneously: it acts as an adhesion promoter between the conductive material and the low-k dielectric material, serves as a diffusion barrier to prevent metal contamination, and provides a controlled interface for subsequent deposition processes. This multi-functionality reduces the need for separate etch stop layers, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces RC delay, enhances the stability and adhesion of interconnects, and improves the overall performance of semiconductor devices by preventing metal diffusion and ensuring good contact between conductive features and dielectric layers.
Implementation Method 1
surface treatment to modify the surface energy of the dielectric layer
Implementation Method 2
barrier layer formed on the dielectric layer... preventing metal diffusion
Data Source
AI summary
An interconnect structure includes a first conductive feature, a first dielectric layer a first etch stop layer, a second etch stop layer, a second dielectric layer, and a second conductive feature. The first etch stop layer is disposed over the first conductive feature and the first dielectric layer. The second etch stop layer is disposed on the first etch stop layer. The second dielectric layer is disposed on the second etch stop layer. The second conductive feature includes a first conductive layer and a first barrier layer. The first conductive layer extends through the second dielectric layer, the second and the first etch stop layers to contact to the first conductive feature. The first barrier layer is sandwiched between the first conductive layer and the second dielectric layer, the first conductive layer and the second etch stop layer, and between the first conductive layer and the first etch stop layer.