Interconnect Barrier Deposition Using SAM-Blocked Via Bottoms
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Solution Overview
Problem
As microelectronic devices scale to the 3 nm node and beyond, interconnect via resistance increases significantly due to the high resistivity of barrier layers, leading to performance throttling and increased power consumption, necessitating improved methods for selective deposition of materials during interconnect structure formation.
Innovation Solution
The method involves forming a dielectric layer with a gap, pre-cleaning the metal surface, selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap, and then depositing a barrier layer only on the sidewalls, while preventing its deposition on the metal surface, followed by removing the SAM to reduce via resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is deposited on the sidewalls to prevent copper diffusion, then adhesion and diffusion prevention are improved, but via resistance increases due to the high resistivity of the barrier layer
Solution Approach 1:
The barrier layer deposition is segmented into two distinct phases: (1) deposition on sidewalls only to provide adhesion and diffusion barrier functions, and (2) selective prevention of deposition on the metal surface to maintain low via resistance. This segmentation allows each surface to have optimized properties for its specific function.
Solution Approach 2:
Different surfaces are given different qualities through selective barrier layer deposition. The sidewalls receive the barrier layer for adhesion and diffusion prevention, while the metal surface at the bottom remains barrier-free to maintain low electrical resistance. This local differentiation resolves the contradiction between needing barrier properties and maintaining conductivity.
2Object-affected harmful factors
If the thickness of barrier layers is reduced to decrease via resistance, then via resistance decreases, but adhesion and diffusion prevention capability deteriorates
Solution Approach 1:
The solution applies local quality by making the barrier layer thickness location-dependent: thick enough on sidewalls to provide adequate adhesion and diffusion barrier, but absent entirely on the metal surface to minimize resistance. This spatial variation in barrier layer properties resolves the contradiction between protective function and electrical conductivity.
3Manufacturing precision
If a self-assembled monolayer is deposited on the bottom of the gap to enable selective barrier layer deposition, then selectivity improves, but process complexity increases
Solution Approach 1:
A self-assembled monolayer (SAM) is introduced as an intermediary substance that selectively adsorbs on the metal surface, preventing barrier layer deposition in the via bottom region. This intermediary enables precise spatial control of barrier layer formation, achieving high selectivity despite the additional process step.
Solution Approach 2:
The self-assembled monolayer is deposited in advance before the barrier layer deposition process. This preliminary action prepares the surface with selective adsorption properties, ensuring that subsequent barrier layer deposition occurs only in desired locations (sidewalls) and not on the metal surface, thereby achieving precise control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the selectivity of the self-assembled monolayer, reduces the formation of barrier layers on the metal surface, and thereby decreases via resistance, enhancing the performance of interconnects in microelectronic devices.
Implementation Method 1
selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and the metal surface
Implementation Method 2
The SAM blocks deposition of the barrier layer on the metal surface
Data Source
AI summary
Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A pre-clean process is performed before a self-assembled monolayer (SAM) is formed on the bottom of the gap. A barrier layer is selectively deposited on the sidewalls but not on the bottom of the gap. The SAM is removed after selectively depositing the barrier layer on the sidewalls.