Multi-Voltage Interconnect BER Margining for PAM-4 Links
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Solution Overview
Problem
As data rates in serial interconnects increase, maintaining a bit error rate (BER) of 10−12 or better becomes challenging due to cross-talk, inter-symbol interference, and channel loss from components like sockets, vias, and add-in cards, especially with the deployment of PAM-4 encoding for next-generation data rates such as PCIe Gen 6, where the target BER is higher at 10−6.
Innovation Solution
The implementation of mechanisms and logic circuitry to address error bursts on each lane and across lanes, including the use of retimers, forward error correction (FEC) with Error Correcting Code (ECC) and Cyclic Redundancy Check (CRC), and a common physical layer (PHY) to support multiple interconnect protocols like PCIe, CXL, and UPI, which can dynamically adjust to variations in error correlation and system conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rates in serial interconnects are increased to achieve higher productivity, then productivity is improved, but bit error rate deteriorates due to cross-talk, inter-symbol interference, and channel loss
Solution Approach 1:
The patent applies preliminary action by performing channel characterization and error margining before actual data transmission. The system pre-measures the error characteristics of each lane using training sequences, establishes error budgets, and configures FEC parameters in advance. This allows the system to proactively compensate for anticipated errors at higher data rates rather than reactively correcting them during transmission.
Solution Approach 2:
The patent implements feedback mechanisms through continuous monitoring of error rates and channel conditions during operation. The system uses feedback from error counters, BER measurements, and channel quality indicators to dynamically adjust FEC parameters, retrain lanes, or switch to alternative encoding schemes. This closed-loop control enables the system to maintain reliability at high data rates by adapting to changing channel conditions.
2Productivity
If PAM-4 encoding is deployed to achieve higher data rates, then productivity is improved, but reliability deteriorates with a higher target BER of 10^-6
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting FEC code rates, interleaving depths, and equalization parameters based on the specific channel conditions and PAM-4 signal characteristics. The system modifies these parameters per-lane and per-direction to optimize the trade-off between throughput and error rate, allowing reliable PAM-4 operation at 64 GT/s and beyond.
3Productivity
If the number of lanes is increased to achieve higher bandwidth, then productivity is improved, but reliability deteriorates due to cross-talk and inter-symbol interference
Solution Approach 1:
The patent applies segmentation by treating each lane as an independent channel with its own error characteristics, enabling per-lane characterization and margining. The system divides the total error budget across lanes and applies lane-specific FEC configurations. This granular approach allows the system to manage cross-talk and interference effects on individual lanes while maintaining overall link reliability at high lane counts.
4Reliability
If forward error correction with ECC and CRC is implemented to improve reliability, then bit error rate is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by implementing a common physical layer architecture that supports multiple interconnect protocols (PCIe, CXL, UPI) with unified FEC and error handling mechanisms. The same hardware infrastructure handles both traditional PCIe error correction and the enhanced error protection requirements of PAM-4 protocols, reducing overall system complexity despite the advanced error correction capabilities.
Data Source
AI summary
Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.