Semiconductor Interconnect Filling With Alternating Bias Sputtering
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Solution Overview
Problem
As semiconductor devices integrate more densely, the narrow line widths of metal interconnections pose challenges during metal deposition, leading to potential clogging of recessed regions and the formation of voids, which can hinder stable device operation.
Innovation Solution
A method involving alternating sputtering deposition processes with different bias voltages is employed to form a metal layer within the recessed region. The first sputtering process uses a low bias voltage to deposit a sacrificial metal pattern, while the second process, with a higher bias voltage, etches the first portion and resputters the second portion to fill the recess, repeating this process to achieve the desired thickness and prevent clogging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If metal deposition is performed in narrow recessed regions, then metal interconnections with fine line widths can be formed, but the entrance of the recessed region may be clogged and voids may form
Solution Approach 1:
The patent employs periodic alternation between low bias voltage deposition (filling mode) and high bias voltage deposition (etching mode) to prevent clogging and void formation. This periodic switching allows the metal layer to be deposited in a controlled manner, where the low bias voltage fills the recessed region while the high bias voltage periodically removes excess material from the entrance, preventing clogging and ensuring reliable deposition in narrow recessed regions
Solution Approach 2:
The patent changes the bias voltage parameter during the deposition process to control the deposition morphology. By switching between low bias voltage (for filling) and high bias voltage (for etching and preventing clogging), the deposition characteristics are dynamically adjusted to maintain both fine line width precision and deposition reliability in narrow recessed regions
2Reliability
If the bias voltage is increased to prevent clogging, then metal can be deposited in the recessed region, but the first metal pattern is etched and requires resputtering
Solution Approach 1:
The periodic alternation between low and high bias voltage deposition cycles allows the system to overcome the productivity loss from etching. During low bias voltage phases, metal is efficiently deposited; during high bias voltage phases, excess material is removed to prevent clogging. This periodic cycle optimizes the balance between preventing clogging and maintaining overall deposition efficiency
Solution Approach 2:
The patent converts the harmful effect of high bias voltage (etching the deposited metal) into a beneficial process. The etching action during high bias voltage phases prevents clogging at the entrance of recessed regions, and the subsequent low bias voltage phases redeposit metal to compensate for the etched material, ultimately improving deposition reliability without significant loss in productivity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents clogging and ensures uniform metal deposition within the narrow recessed regions, enhancing the reliability and stability of semiconductor devices by maintaining the integrity of metal interconnections.
Implementation Method 1
performing a first sputtering deposition process using a first bias voltage to form a first metal pattern
Implementation Method 2
forming a second metal layer on the first metal layer using electroplating
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a dielectric layer on a lower structure. The method includes forming an opening to penetrate through the dielectric layer. The method includes alternately repeating a first operation, in which a first sputtering deposition process is performed to form a first metal pattern in the opening, and a second operation, in which a second sputtering deposition process is performed to form a second metal pattern in the opening, two or more times to form a first metal layer. The method includes forming a second metal layer on the first metal layer in an electroplating manner, and planarizing the first and second metal layers. Moreover, first and second process times, during which the first sputtering deposition process and the second sputtering deposition process, respectively, are performed, are each about five seconds or less.