Serial Differential Interconnect for Blocking Link State PHY Tasks
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in meeting the increasing demand for bandwidth and power efficiency, particularly in servers and mobile devices, as they struggle to scale with the growing complexity of computing systems and the need for faster communication between multiple processors and devices.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and a coherence protocol to manage data transfer and ensure reliable communication across multiple devices, while also incorporating power management and error handling mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but communication speed and bandwidth are insufficient
Solution Approach 1:
The interconnect architecture is segmented into multiple independent point-to-point links instead of a shared multi-drop bus. Each link connects specific devices directly, enabling parallel communication paths that increase bandwidth and speed while maintaining manageable complexity through modular design
Solution Approach 2:
The architecture transitions from a single shared communication dimension (multi-drop bus) to multiple parallel communication dimensions (point-to-point links with virtual channels). This dimensional expansion allows simultaneous data transfer across multiple paths, dramatically improving throughput and speed
2Productivity
If multiple physical processors and cores are added to increase processing power, then computing capability is improved, but communication requirements and interconnect complexity increase
Solution Approach 1:
The point-to-point interconnect links are designed to be universal, supporting multiple functions including data transfer, error correction, flow control, and power management. This multi-functionality reduces the need for separate dedicated communication infrastructure for each function, thereby managing complexity while supporting multiple processors
Solution Approach 2:
The patent introduces intermediary components such as flow control mechanisms and error correction protocols that mediate between processors and memory devices. These intermediaries simplify the overall communication infrastructure by providing standardized interfaces and protocols that reduce direct complexity between multiple processors
3Productivity
If data transfer speed is increased to meet communication demand, then processing efficiency is improved, but power consumption increases
Solution Approach 1:
The interconnect architecture implements dynamic power management where power consumption is adjusted based on actual data transfer requirements. The system can dynamically enable or disable communication paths and adjust transfer rates depending on workload demands, thereby maintaining high transfer efficiency when needed while reducing power consumption during low-activity periods
Solution Approach 2:
The patent extracts and separates power management functions from the core data transfer path, allowing independent optimization of power consumption. By taking out power control mechanisms as separate manageable components, the system can optimize data transfer speed for performance without proportionally increasing overall power consumption
4Quantity of substance
If point-to-point links with multiple virtual channels are implemented, then bandwidth and communication speed are improved, but error detection and control complexity increase
Solution Approach 1:
The protocol stack is segmented into distinct layers, each handling specific functions: physical layer for signal transmission, data link layer for error detection, and higher layers for flow control and routing. This segmentation allows complex protocols to be managed through modular, independent components that can be designed and verified separately
Solution Approach 2:
The patent implements preliminary error detection and flow control mechanisms that act before data transfer issues occur. By performing error checking and flow management in advance through virtual channel allocation and credit-based flow control, the system prevents errors from propagating through the complex multi-channel architecture, simplifying overall control
Data Source
AI summary
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.