Serial Differential Interconnect Blocking States for PHY Link Tasks
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in meeting the increasing demand for bandwidth and performance while balancing power consumption, particularly as the number of processing devices and complexity of components grow, leading to inefficiencies in communication between sockets and devices.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that employs a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and a coherence protocol to manage data transfer and ensure reliable communication across multiple devices, enabling efficient data transfer and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of processing devices and complexity of components increase to meet bandwidth demand, then data transfer capacity is improved, but power consumption increases
Solution Approach 1:
The interconnect architecture is segmented into multiple independent virtual channels (e.g., 8 virtual channels) that can operate simultaneously. Each virtual channel can transfer data independently, allowing the system to achieve high aggregate bandwidth by activating only the necessary number of channels rather than requiring all channels to operate at full power continuously.
Solution Approach 2:
The system dynamically adjusts the number of active virtual channels based on actual data transfer requirements. The interconnect can transition between different operational states (e.g., 1-channel mode, 2-channel mode, up to 8-channel mode) to match the bandwidth demand, thereby reducing power consumption when maximum capacity is not required.
2Device complexity
If traditional multi-drop buses are used for electrical communications, then device complexity is reduced, but communication performance and bandwidth are insufficient
Solution Approach 1:
The traditional single bus structure is segmented into multiple independent virtual channels, each capable of carrying data simultaneously. This segmentation allows parallel communication paths that dramatically increase bandwidth while maintaining a relatively simple point-to-point connection structure for each channel.
Solution Approach 2:
The system transitions from a single-dimensional bus architecture to a multi-dimensional virtual channel architecture. By introducing virtual channel identifiers and multiple parallel transmission paths, the system achieves higher communication capacity without significantly increasing the physical complexity of individual connection components.
3Productivity
If more virtual channels are added to increase bandwidth, then data transfer efficiency is improved, but flow control complexity increases
Solution Approach 1:
The system implements feedback-based flow control where receiving endpoints send credit signals back to transmitting endpoints to indicate available buffer space. This feedback mechanism automatically regulates data flow across multiple virtual channels without requiring complex centralized control, as each channel independently responds to feedback from its destination.
Solution Approach 2:
Credit-based flow control acts as an intermediary mechanism between the data transmission layer and the buffer management layer. The credit signals serve as mediators that coordinate data flow across multiple virtual channels, simplifying the overall flow control complexity by using a standardized credit/debit protocol rather than complex per-channel arbitration logic.
Data Source
AI summary
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.