On-Chip Interconnect Bridge Cut-Through Latency
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Solution Overview
Problem
Standard bus interfaces in multiprocessor system-on-chip (SOC) platforms face challenges with write transactions being non-precise due to potential master inserted wait states, leading to increased latency and buffering requirements, disrupting the processing pipeline of peripherals like external memory interfaces.
Innovation Solution
Incorporating a single bit attribute signal to indicate whether master inserted wait states will occur during burst transactions, allowing for cut-through bridging that adheres to standard bus protocols while minimizing buffering and latency, by enabling or disabling wait states based on transaction attributes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If master inserted wait states are allowed in standard bus interfaces, then bus protocol compliance is maintained, but write transaction precision is compromised and latency increases
Solution Approach 1:
The bus transaction protocol is segmented into two independent parts: the command phase (which maintains standard protocol compliance with wait states) and the data phase (which implements precise cut-through bridging). This segmentation allows each phase to optimize for its specific requirements without compromising the other.
Solution Approach 2:
The bridge receives and processes the command phase of the transaction in advance, determining whether master inserted wait states will occur before the data phase begins. This preliminary action allows the bridge to prepare appropriate buffering strategies beforehand, ensuring precise write transactions when needed while maintaining protocol compliance when wait states are present.
2Adaptability or versatility
If store and forward buffering is implemented to handle master inserted wait states, then protocol compliance is maintained, but latency increases and area requirements increase
Solution Approach 1:
The bridge implements dynamic buffering behavior that adapts to the specific transaction characteristics. Instead of always using store and forward buffering, the bridge dynamically determines whether cut-through bridging is appropriate based on the transaction type and master inserted wait state attributes, optimizing latency when possible while maintaining protocol compliance when necessary.
Solution Approach 2:
The bridge changes its operational parameters (buffering vs. cut-through) based on transaction attributes such as master inserted wait state indicators. This parameter change allows the system to switch between latency-optimal cut-through mode and protocol-compliant buffering mode as needed.
3Adaptability or versatility
If store and forward buffering is used for all transactions, then protocol compliance is ensured, but area requirements increase
Solution Approach 1:
Instead of implementing store and forward buffering for all transactions (excessive action), the bridge applies buffering only partially - specifically only when master inserted wait states are detected and protocol compliance requires it. This partial application of buffering reduces the required area while maintaining protocol compliance for necessary cases.
Data Source
AI summary
A method for performing write transactions in an interconnect fabric is described. A burst write transaction is received by a bridge coupled to a master. The burst transaction is initiated by a command phase that includes a wait state attribute. The bridge is also coupled to a second bus that is coupled to a slave destination device or to another bridge. The bridge may initiate a cut-through transaction to the second bus when the wait state attribute indicates a master inserted wait state will not be incurred during the burst transaction.