Interconnect Bridge With Integrated Passives for Compact SiP Packaging

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Solution Overview

Problem

Semiconductor devices face challenges in interconnecting multiple semiconductor die within a system-in-package (SiP) module and finding sufficient footprint space for integrated passive devices.

Innovation Solution

The integration of an interconnect bridge with integrated passive devices (IPDs) is formed over a substrate using common semiconductor manufacturing steps, allowing IPDs to be easily integrated onto semiconductor die, reducing the need for external discrete passive components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If discrete passive devices are used in SiP modules, then electrical functions can be supported, but footprint space is insufficient and device complexity increases

Engineering Contradiction:
Improvefootprint spaceVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent merges the interconnect bridge structure with passive device functionality into a single integrated structure. The passive devices (resistors, capacitors, inductors) are formed directly within the interconnect bridge layers, combining what were previously separate components into one unified element that reduces footprint and simplifies the overall device architecture

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The interconnect bridge is designed to serve multiple functions simultaneously: it provides electrical interconnection between semiconductor die and incorporates passive devices for signal processing, filtering, and impedance matching. This multi-functional approach eliminates the need for separate discrete passive components

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Area of stationary object

If integrated passive devices are formed over semiconductor die, then footprint space is optimized, but manufacturing complexity increases

Engineering Contradiction:
Improvefootprint spaceVSAvoidmanufacturing complexity
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The passive devices are formed during the same manufacturing process steps as the interconnect bridge, before final assembly. Conductive layers are deposited and patterned to create both the interconnect pathways and passive device structures in advance, integrating passive device fabrication into the existing manufacturing flow rather than adding separate processing steps

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes variations in conductive layer thickness, material composition, and geometric configuration to create different passive device types (resistors, capacitors, inductors) from the same base manufacturing process. By changing physical and chemical parameters of the conductive layers, multiple passive device functions are achieved without requiring different manufacturing processes

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260053018A1Semiconductor Device and Method of Making an Interconnect Bridge with Integrated Passive Devices
Publication Date: 2026.02.19 STATS CHIPPAC LTD
  • US20260053018A1 patent drawing
  • US20260053018A1 patent drawing
  • US20260053018A1 patent drawing

AI summary

A semiconductor device has a first substrate. A first semiconductor die and second semiconductor die are disposed over the substrate. An interconnect bridge is disposed over the first semiconductor die and second semiconductor die. The interconnect bridge has a second substrate. A conductive trace is formed over the second substrate. The conductive trace is electrically coupled from the first semiconductor die to the second semiconductor die. An IPD is also formed over the second substrate. The IPD is electrically coupled between the first semiconductor die and second semiconductor die. An encapsulant is deposited over the first substrate, first semiconductor die, second semiconductor die, and interconnect bridge.