Interconnect Bridge With Integrated Passives for Compact SiP Routing
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Solution Overview
Problem
Semiconductor devices face challenges in interconnecting multiple semiconductor die within a system-in-package (SiP) module due to limited footprint space for passive elements, and discrete passive devices require additional space outside the die.
Innovation Solution
The integration of integrated passive devices (IPDs) is achieved through a process that forms passive components over a substrate using common semiconductor manufacturing steps, creating an interconnect bridge with through-silicon vias and conductive traces to connect semiconductor die, optimizing footprint usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If discrete passive devices are used, then electrical functionality is achieved, but footprint space increases
Solution Approach 1:
The patent merges passive devices (resistors, capacitors, inductors) directly onto the semiconductor die using standard semiconductor fabrication processes. This integration eliminates the need for separate discrete passive devices and their associated packaging, interconnectors, and mounting structures, thereby dramatically reducing the overall footprint while maintaining full electrical functionality.
Solution Approach 2:
The patent utilizes the third dimension (vertical depth) of the semiconductor die by forming passive devices through multi-layer deposition and etching processes. Conductive layers are stacked in multiple levels with vias providing vertical interconnects, allowing passive devices to occupy vertical space rather than only horizontal footprint, thereby reducing the area required on the die surface.
2Area of stationary object
If integrated passive devices are formed over semiconductor die, then footprint space is optimized, but manufacturing complexity increases
Solution Approach 1:
The patent employs universal semiconductor fabrication processes (photolithography, chemical vapor deposition, physical vapor deposition, etching, sputtering, electroplating) that are already standard in the industry. These multi-functional processes can form both active semiconductor devices and passive devices (resistors, capacitors, inductors) using the same toolset and material deposition techniques, thereby avoiding the need for specialized manufacturing equipment or processes.
Solution Approach 2:
The patent utilizes parameter changes in material properties and process conditions to differentiate passive device formation from active device fabrication. By adjusting deposition thickness, pattern geometry, and etch selectivity, the same fabrication processes can create resistors, capacitors, and inductors with varying electrical characteristics, thereby managing manufacturing complexity through controllable process parameters rather than requiring fundamentally different manufacturing approaches.
3Adaptability or versatility
If multiple semiconductor die are interconnected, then system functionality is enhanced, but interconnection complexity increases
Solution Approach 1:
The patent introduces an intermediary substrate that serves as a platform for mounting multiple semiconductor die and providing routing layers for interconnections. This intermediary structure mediates between the individual die and the final system architecture, allowing complex interconnection patterns to be implemented through standardized substrate mounting and wiring techniques rather than requiring direct complex bonding between all die pairs.
Solution Approach 2:
The patent segments the interconnection architecture into hierarchical levels: intra-die interconnections (within each semiconductor die), inter-die interconnections (between adjacent die on the substrate), and package-level interconnections (to external components). This segmentation allows each level to be optimized independently using appropriate techniques, thereby managing overall interconnection complexity through modular architecture rather than requiring a monolithic complex connection scheme.
Data Source
AI summary
A semiconductor device has a first substrate. A first semiconductor die and second semiconductor die are disposed over the substrate. An interconnect bridge is disposed over the first semiconductor die and second semiconductor die. The interconnect bridge has a second substrate. A conductive trace is formed over a first surface of the second substrate. The conductive trace is electrically coupled from the first semiconductor die to the second semiconductor die. A conductive via is formed through the second substrate. An IPD is formed over a second surface of the second substrate. The IPD is electrically coupled to the first semiconductor die or second semiconductor die through the conductive via. An encapsulant is deposited over the first substrate, first semiconductor die, second semiconductor die, and interconnect bridge.