Interconnect Bridge Pad Layout for Package Alignment Tolerance
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Solution Overview
Problem
Challenges in semiconductor chip packaging include unwanted material interactions, precision and scaling requirements, power delivery, limited failure tolerance, and manufacturing costs, particularly in high-performance computing applications with increased package form-factor demands and misalignment issues in interconnect bridges.
Innovation Solution
The implementation of interconnect bridges with through-bridge vias (TBVs) and differential landing pad sizes for alignment, using fiducials for precise assembly, and thermocompression bonding to enhance connectivity and reduce misalignment errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnect bridges are used to provide interconnections between semiconductor chips, then connectivity and performance are improved, but misalignment and overlay errors occur during assembly
Solution Approach 1:
The patent applies asymmetry by creating differential landing pad sizes on the interconnect bridge. The first landing pad has a different size than the second landing pad, which allows for compensating alignment errors in different directions. This asymmetric design enables the larger landing pad to accommodate misalignment while the smaller pad maintains precise electrical connection, thus resolving the contradiction between connectivity and alignment precision.
Solution Approach 2:
The patent implements preliminary action by pre-positioning fiducial markers on the interconnect bridge before assembly. These fiducials are used to establish reference frames and guide alignment during the bonding process. By preparing alignment references in advance, the system can compensate for potential misalignment issues, improving both connectivity reliability and manufacturing precision.
2Productivity
If package form-factor is increased to accommodate more chips and HBM units, then computing performance is improved, but material interactions and manufacturing complexity increase
Solution Approach 1:
The patent applies segmentation by dividing the large package into modular components: multiple semiconductor chips, multiple HBM units, and interconnect bridges that segment the connection pathways. This modular segmentation allows the complex package to be manufactured and assembled in manageable sections, reducing overall manufacturing complexity while maintaining high computing performance through parallel processing capabilities.
Solution Approach 2:
The interconnect bridge serves as an intermediary component between the semiconductor chips and HBM units. It provides a standardized interface that simplifies the connections in the large package, acting as a mediator that reduces manufacturing complexity by establishing repeatable connection patterns across multiple components, thereby enabling high-performance computing without proportionally increasing manufacturing difficulty.
3Power
If through-bridge vias are used to enhance interconnect functionality, then power delivery and connectivity are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies the nested doll principle by placing the through-bridge via structures within the interconnect bridge substrate, which itself is integrated into the larger package assembly. The via structures are nested within the bridge substrate, and the bridge is nested within the overall package with multiple chips and HBM units. This nesting allows power delivery pathways to be embedded within the structure, improving power delivery while the hierarchical nesting reduces the impact of via alignment errors on the overall system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves packaging yields and performance by reducing overlay errors and misalignment, enabling efficient power delivery and heterogeneous integration in semiconductor chips.
Implementation Method 1
thermocompression bonding to enhance connectivity and reduce misalignment errors
Data Source
AI summary
Semiconductor chip package substrates having interconnect bridges, assemblies including these semiconductor chip package substrates, and methods of manufacturing interconnect-bridge-containing semiconductor package chip substrates are provided. The interconnect bridges can include through-bridge vias that are electrically coupled to the semiconductor package substrate. The embedded bridges can be aligned to fiducials within the semiconductor package substrate.